JPS63107327A - Time division multiplex transmission equipment - Google Patents

Abstract

PURPOSE:To send data with high accuracy even with a clock of ordinary accuracy by detecting an error of data reception due to the deviation of clock at the sending side and the receiving side before a load control signal is generated and controlling the load in fail-safe. CONSTITUTION:A piece of time division multiplex transmission equipment is provided with a transmitter 5 having a prescribed period of clock, a receiver 6 having a prescribed period of clock and connected to the transmitter 5 via a communication line 2, and a synchronizing signal generating means using the clock of the transmitter 5, specifying a master synchronizing period and a data transmission channel succeeding thereto and giving a synchronizing signal relating to the regulation to the transmitter 5 and the receiver 6, and the data is sent at each channel based on the synchronizing signal, and whether or not the relative deviation of the clock of the transmitter 5 is increased to cause a fault in the data transmission is discriminated at the master synchronizing period based on the clock of the receiver 6 and when it is discriminated to be large, the data received by the receiver 6 is not outputted. That is, the relative deviation of the clocks of the transmitter/receiver is detected and the data having the possibility of erroneous reception is not outputted.

Description

[Detailed description of the invention] [Industrial application field 1 The present invention relates to a time division multiplex transmission device.

[Prior Art] An example of a conventional time division multiplex transmission device is one shown in US Pat. No. 4,370.561.

This consists of a multiplex communication timing unit 1~ and a transmitting/receiving unit connected to this via a control signal line, and the timing unit defines a master synchronization period and a number of data channels following this. and ret the number of channels of the transmitter/receiver unit in the master synchronization period,
Data is transmitted sequentially through each channel.

However, in these conventional time division multiplex transmission devices, each transmitter/receiver unit l~ has a separate clock, and asynchronous data transmission is performed on each data channel, so there is a large period between the two clocks. If a deviation occurs, there is a possibility that an error will occur in data transmission, and the load connected to the time division multiplex transmission apparatus may be erroneously controlled.

If the load is incorrectly controlled in a vehicle, for example, the headlights may suddenly turn off at night, or the taillights or backlights may suddenly turn off, which can be extremely dangerous. .

For this reason, conventional time division multiplex transmission systems require each unit to be provided with an extremely high precision clock. However, providing each of a large number of transmitting/receiving units with a high-precision clock is difficult in terms of cost, and is far from perfect.

[Object of the Invention] It is an object of the present invention to provide an hour/minute v1 multiplex transmission device which can improve the above-mentioned problems and can perform highly accurate data transmission even with a clock with perfect accuracy.

[Summary of the Invention] In order to achieve the above object, the present invention includes a time division multiplex transmission device including a transmitter having a clock with a predetermined period, and a transmitter having a clock with a predetermined period and connected to the transmitter via a communication line. a periodic signal generating means for defining a master synchronization period and a subsequent data transmission channel using a clock of the transmitter and supplying a synchronization signal according to the regulation to the transmitter and the receiver; A data transmission means that performs data transmission in each channel based on a signal, and a relative shift between a clock on the transmitter side with respect to the m1 meter on the receiver side in the master synchronization period, which affects the data transmission of the data transmission means. A transmitting/receiving device comprising a determining means for determining whether the data has become large enough to cause an abnormality, and a data resetting means for not outputting the data received by the receiver when the determining means determines that the data has become large enough to cause an abnormality. By detecting the relative deviation of the machine's time reduction, data that is likely to be received incorrectly is not output.

[Example] Hereinafter, the present invention will be described in detail using the accompanying drawings.

FIG. 951 is a circuit diagram of a time division multiplex transmission device according to an embodiment of the present invention, and FIGS. 2 and 3 are detailed diagrams of the transmitting circuit and receiving circuit of the device.

As shown in FIG. 1, the time division multiplex transmission 5A device shown in this example has a power line 1 and a communication line 2, and a system in which a data signal and a synchronization signal are superimposed on the communication line 2. 1 is connected to a vehicle power source 4 via a circuit protector 3 such as a fuse.

A transmitter 5 and a receiver 6 are connected to the power line 1 and the communication line 2. The transmitter 5 is placed, for example, in an instrument panel of the driver's seat, and the receiver 6 is placed, for example, in a trunk room at the rear of the vehicle.

The transmitter 5 includes a power supply circuit 7 and a transmission circuit 8 therein.
and a signal output circuit 9.

The power supply circuit 7 is composed of a resistor 10 inserted between the power supply line 1 and the transmission circuit 8, and a diode 11 and a capacitor 12 inserted in parallel between the resistor 10 and the ground. Supply voltage vDD to circuit 8 and signal output circuit 9
It provides:

The transmitting circuit 8 is connected to external switches 13 through terminals 1° to 7, and receives 8-bit data from the terminals 1o=Iy at a predetermined timing, converts the taken data into serial data, and outputs a signal at a predetermined timing. Output terminal (O
IJT). Details of the transmitting circuit 5 will be explained with reference to FIG. The signal output circuit 9 is an N-chi 1 cine MO connected to the signal output terminal (OUT>).
It is composed of an 8FET 14, an output protection resistor 15, an input-capable resistor 16, and a capacitor 17, and changes the signal level of the communication line 2 according to the signal input from the signal output terminal (OUT>. That is, When a high level signal is output from the signal output terminal (OUT), the signal output circuit 9 makes the FET 14 conductive and changes the signal level of the communication line 2 from the power supply potential VDD to the ground potential (low level).
It plays the role of reducing the

On the other hand, the receiver 6 includes a signal input circuit 18, a receiving circuit 19 into which the output of the circuit 18 is input via a signal input terminal (IN), and a power supply circuit 20. The four components of the power supply circuit 20 are the same as the power supply circuit 7 of the transmitter 5.

The signal input circuit 18 is composed of a pull-up resistor 21 and an input protection resistor 22, and is connected to the communication line 2 via the resistor 22.
This signal is given to the receiving circuit 19.

The receiving circuit 19 reads the signal state of the communication line 2, outputs a load control signal of a predetermined level from the terminals θ0 to θ7 based on the operating state of the switches 13, and outputs a load control signal of a predetermined level from the terminals θ0 to θ7.
24 to control loads 25. Details of the receiving circuit 19 will be explained with reference to FIG.

As shown in FIG. 2, the transmission circuit 8 includes an oscillation circuit 26,
It has a transmission control circuit 27, a synchronous control circuit 28, two latch/shift register circuits, and a PWM encoder 30, and the outputs of the synchronous circuit 28 and PWM encoder 3.1 are connected by an OR circuit 31. is configured to send the output of the signal via the buffer 32 to the signal output terminal (OUT>).

The transmitting circuit 26 transmits a clock signal of a predetermined period and outputs it to the transmission control means 27 and the synchronization control means 28. However, this clock signal may cause an error ε1 due to aging, temperature changes, and the like.

The transmission control circuit 27 receives the clock signal output from the transmission circuit 26 and performs general transmission control based on the control pattern shown in FIG. 4(a).

In the control pattern shown in FIG. 4(a), a master synchronization period with a width TM is followed by multiple channels CH with a time width TS.
o to CH7.

However, the time widths TM and TS shown here are the transmission circuit 26.
This is defined as the case where there is no error in the clock signal (ε1-0).

The synchronous control circuit 8 generates a synchronous control signal S shown in FIG. 4(b) based on the synchronous control command signal from the transmission control circuit 27.
It outputs 1. This synchronization control signal S1 is normally at a low level, and rises to a high level for a predetermined short time TO from the start time of each data channel. When this signal S1 is outputted from the signal output terminal (OUT> to the gate of FETI 4 via the OR circuit 31 and buffer 32, the signal is inverted by the FET 14, and the signal S1 is outputted on the communication line 2 as shown in FIG. A signal S2 shown in C) appears.

Here, the illustrated symbol FLT is a section for data transmission whose level can be lowered by grounding the communication line 2 by other means (hereinafter, this section is referred to as a float section).
It is. The end time of the float section FLT is a time TF after the channel start time.

The latch/shift register circuit 29 is connected to the transmission control circuit 27.
A data latch command signal is received at the beginning time of the master synchronization period, and data ``10101011J'', for example, is latched according to the signal states of data input terminals 1° to I7.

Data "1" indicates that the corresponding switch of the switches 13 is on, and data "0" indicates that the corresponding switch is off.

The PWM encoder 30 receives a data output command signal from the synchronization control circuit 27 at the start time of each data channel,
As shown in FIG. 4(d), in each float period FLT, the data "11" or "rOJ" stored in the latch/shift register circuit 29 is changed to a high level or low level signal S.
Convert to 2 and output.

The OR gate 31 receives the signal S shown in FIGS. 4(b) and 4(d).
1. Take the logical sum 81 +83 of S3 and use this as FETI
Output to 4. Therefore, on the communication line 2, as shown in FIG.
A PWM signal S4 as shown in FIG.

On the other hand, one receiving circuit receives the PWM signal S4 of the communication line 2.
Filter 3 inputs from the input terminal (IN> and shapes the waveform)
3, and a channel detection circuit 3 connected to the filter 33.
4 and a PWM decoder 35. The channel detection circuit 34 is connected to a transmission circuit 36 and a reception control circuit 37.

An 8-bit shift register 38 is arranged between the PWM decoder 35 and the reception control circuit 37, and the register 38
are connected to a data latch circuit 39, and the three latch circuits are connected to 8-bit output terminals 00 to .theta.7.

The oscillation circuit 36 has the same configuration as the oscillation circuit 26 on the transmission circuit 8 side, and outputs a clock signal of a predetermined frequency.

However, like the oscillation circuit 26, the clock signal may cause an error ε2 due to temperature changes or the like.

The channel detection circuit 34 reads the signals on the communication line 2 shown in FIG. 4<e> and forms the following three types of signals.

■ Marker detection signal MD This signal MD is an internal signal for resetting the channel, and the signal S4 shown in FIG. It is formed when the Time Tuo
This will be explained in detail in FIG.

■Data output reset signal DR This signal DR indicates that the signal on the communication line 2 is abnormally long for a period of time T D starting from the start time t7 of the 8th channel CH7.
This is a signal that detects that RVc is at a high level and outputs fail-safe data without outputting the received data that one of the reception circuits is receiving. Time TD
R will be explained in detail in FIG.

(2) The signal SC of the channel start signal S is a signal generated in synchronization with the start time of each channel.

The reception control circuit 37 receives the channel start signal SC or data reset signal DR output from the channel detection circuit, and controls the shift register 38 and the data latch circuit 39 in each tuning period.

The PWM decoder 35 reads the current state of the signal S4 on the communication line 2 shown in FIG. 4(e) and sets the low level to "1".
”, the high level is rewritten to rOJ data.

The shift register 38 synchronizes with the signal rise timing (indicated by an arrow) of the data read signal S5 from the reception control circuit 37 shown in FIG. Extract ``1'' or ``0'',
Data is stored while being shifted one bit at a time for each channel. Therefore, the 8-bit shift 1 register 37 receives the 8-bit data input from the data input terminal 1o"□I7, for example "10101011".
will be restored.

The data latch circuit 39 receives data latch command signals DL1. :W, shift register 3
8 data is received and load control signal output terminal 0
It outputs a load control signal from 0 to θ7. Here, the data "1" or "0" is data for turning on or off the load, and the receiving circuit 19 outputs a high level or low level signal to a predetermined terminal after the data "1" or "0". , the load 25 shown in FIG. 1 is controlled to be turned on or off.

However, the three data latch circuits receive the data reset signal D from the channel circuit 34 via the reception control circuit 37.
When R is received, the load 25 is not controlled using latch data, but the load 25 is controlled using fail-safe data. Fail-safe data is data that has been previously received or data that has been set to fail-safe in advance.

By the way, in this example, the oscillation circuits 26.36 have errors ε1.
ε2, the allowable value of clock error becomes a problem in the data transmission/reception relationship shown in FIGS. 4(e) and 4(g).

Now, in Fig. 4 <a> to (C), TF -4・T
o = J) Ts = 2・TF
...<2) TM=4・TS
Let's try to find the allowable value of the clock error when (3) is set.

FIGS. 5(a) and 5(b) show a floating state and a data detection state when there is no error in both oscillation circuits 26 and 36 (ε1-ε2=o). On the other hand, for these figures, the fifth
Figures <C> and (d) show that the period of the oscillation circuit 26 is +1/3 different from the standard, and the period of the oscillation circuit 36 is 11 times different from the standard.
This shows the situation when there is a deviation of /3.

As is clear from the figure, under equations (1) to (3) above, the allowable value of the period deviation of the oscillation circuit 26, 36 is relatively 2/2 as the transmitter side becomes larger and the receiver side becomes smaller. 3
is the limit.

Therefore, in consideration of such clock errors, in this example, the detection times TMD and TDR of the marker detection signal MD and the data reset signal DR are set as follows.

In Figure 6, (a) is a transmission chart of the master synchronization period when the oscillation circuit 26 has zero error, (b)
The figure is a detection chart of the master synchronization signal and data repit signal when the oscillation circuit 36 has zero error. on the other hand,
In contrast to these figures, figure (Q) is a transmission chart of the master synchronization period when the period error of the oscillation circuit 16 is +ε1,
(d) is a detection chart of the signals MD and OR when the periodic error of the oscillation circuit 36 is -ε2.

Here, in this example, the allowable values for errors in the periods of the oscillation circuits 26 and 36 are both ε0 (for example, 1/3), that is, if the error is ε0 or more, it is within the range where an abnormality occurs in data transmission. Taking the limit value as 60, time T+14D
, TDR was set using the following formula.

Ts (1+2-εO)<TMD< (Ts 10TM>(1-2-εo) ・=(4
)TDR=<Ts+TM)(1+2-80)...
-(5) The above equation (4) is a conditional equation that allows the detection time of the master synchronization interval to be set by setting the relative error tolerance to 2·ε0. Buntake (5) assumes that the relative error tolerance of the oscillation circuit 26.36 is 2ε0, and if the actual error is within this range, then
It can be detected that the high level signal in the master synchronization period is too long, and when the error is exactly the tolerance value 2・ε0, it coincides with the start time of the first channel CHO, and a reception error occurs in the received data. This is a conditional expression for setting a data reset detection time that can detect that there is a possibility that an abnormality has occurred in data transmission.

As described above, in the time division multiplex transmission apparatus shown in this example, the above formula (
Since data reset detection is performed at the time set in step 5), it is possible to detect when the clock cycle deviation of the oscillation circuit provided in the transceiver 5. It is possible to control the load in a fail-safe manner without outputting data that may cause damage.

Note that the calculation start time of each detection signal shown in FIG. 6 is not limited to that shown in the figure, and may be, for example, the end time of the time TO shown in FIG. 4. This invention is not limited to the above embodiments, but can be implemented in other embodiments by making appropriate design changes.

[Effects of the Invention] As described above, according to the time division multiplex transmission device according to the present invention, errors in data reception due to clock lag can be detected before generation of the load control signal, so the load can be fail-safe. By controlling the data transmission quality, data transmission quality can be improved.

[Brief explanation of the drawing]

Each of the drawings shows an embodiment of the present invention; FIG. 1 is a circuit diagram of a time division multiplex transmission device, FIGS. 2 and 3 are detailed diagrams of a transmitting circuit and a receiving circuit, and FIG. 4 is a diagram showing signals of each part. FIG. 5 is a timing chart showing the status, FIG. 5 is an explanatory diagram of the occurrence situation of erroneous reception of data, and FIG. 6 is an explanatory diagram of the timing at which the data reset detection signal is generated. 1...Power supply line 2...Communication line 5...Transmitter 6...Receiver 26...Transmitter side oscillation circuit 36...Receiver side oscillation circuit C)-10 to CH7...・Channel MD...Master synchronization period detection signal DR...Signal to data rehich 1 Agent Patent attorney Yasu Miyoshi 2nd page Figure 8 Figure 5 Figure 6

Claims (1)

[Claims] A transmitter having a clock with a predetermined period, a receiver having a clock with a predetermined period and connected to the transmitter via a communication line, and a master synchronization period and subsequent data transmission using the clock of the transmitter. Periodic signal generation means for defining a channel and supplying a synchronization signal according to the regulation to the transmitter and receiver; a data transmission means for transmitting data on each channel based on the synchronization signal; and a clock on the receiver side. a determining means for detecting a relative deviation of a clock on the transmitter side in the master synchronization period with reference to the master synchronization interval, and determining whether the deviation has become large enough to cause an abnormality in data transmission of the data transmission means; A time division multiplex transmission device comprising: data reset means that does not output the data received by the receiver when the determination means determines that the data has become larger.