JPS63107173A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JPS63107173A JPS63107173A JP25418186A JP25418186A JPS63107173A JP S63107173 A JPS63107173 A JP S63107173A JP 25418186 A JP25418186 A JP 25418186A JP 25418186 A JP25418186 A JP 25418186A JP S63107173 A JPS63107173 A JP S63107173A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- alinas
- alinas layer
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 13
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 16
- 229910000673 Indium arsenide Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 241000321817 Nasa Species 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- -1 aluminum-indium-arsenic Chemical compound 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000000171 gas-source molecular beam epitaxy Methods 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、高周波増幅回路、高速集積回路、光電子集積
回路等に応用される電界効果トランジスタに関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor applied to high frequency amplifier circuits, high speed integrated circuits, optoelectronic integrated circuits, and the like.
［従来の技術］
ヘテロ接合界面に形成される２次元電子を用いたトラン
ジスタとしては、従来より、いくつかのものが提案され
ている。たとえば、特公昭５９−５３７１４、特開昭５
６−４５０７９およびジャパニーズ拳ジャーナル・オブ
・アプライド・フィジックス（Ｊａｐａｎｅｓｅ Ｊ
ｏｕｒｎａｌ ｏｒＡｐｐｌｉｅｄＰｌ＋ｙｓｉｃｓ
）第１９巻、１９８０年、Ｌ２２５頁などに、このタ
イプのトランジスタが記載されている。これらに記載さ
れたトランジスタでは、基板としてガリウム・砒素が用
いられている。ガリウム・砒素を基板として用いた場合
には、室温での２次元電子の移動度は８０００ｃｍ２／
Ｖ−ｓｅＣ程度である。これに対して、インジウム・リ
ン（以下１ｎＰと記す）を基板として用いた場合には、
室温での２次元電子の移動度としては１２００００ｍ２
／■・ｓｅｃ程度が得られる。したがって高周波特性や
増幅率の優れた電界効果トランジスタを実現することが
できる。ＩｎＰを基板として用いる２次元電子トランジ
スタとしては、■ＥＥＥφエレクトロン・デバイス・レ
タース（Ｅｌｃｃｔｒｏｎ Ｄｃｖｉｃｃ Ｌｅｔｔｅ
ｒｓ ） Ｃ，Ｙ、 Ｃｈ ｅ ｎ等。[Prior Art] Several transistors have been proposed in the past that use two-dimensional electrons formed at a heterojunction interface. For example, JP-A-59-53714, JP-A-5
6-45079 and Japanese Journal of Applied Physics (Japanese J
own orAppliedPl+ysics
), Volume 19, 1980, page L225, this type of transistor is described. In the transistors described in these documents, gallium arsenic is used as a substrate. When gallium/arsenic is used as a substrate, the two-dimensional electron mobility at room temperature is 8000 cm2/
It is about V-seC. On the other hand, when indium phosphide (hereinafter referred to as 1nP) is used as a substrate,
The mobility of two-dimensional electrons at room temperature is 120,000 m2
/■·sec can be obtained. Therefore, a field effect transistor with excellent high frequency characteristics and amplification factor can be realized. As a two-dimensional electronic transistor using InP as a substrate, ■EEEφ Electron Device Letters (Elcctron Dcvicc Lette)
rs) C, Y, Chen et al.
ＥＤＬ−３巻、１９８２年、１５２頁に記載されている
ものが知られている。The one described in EDL-3, 1982, page 152 is known.
第２図は、ＩｎＰを基板として用いた従来の２次元電子
トランジスタの構成を示す断面図である。FIG. 2 is a cross-sectional view showing the structure of a conventional two-dimensional electronic transistor using InP as a substrate.
ＩｎＰ基板２１の上には、不純物無添加のアルミニウム
・インジウム・砒素混晶半導体層（以下ＡａＩｎＡｓ層
と＝己す）２２、ガリウム・インジウム・砒素混晶半導
体層（以下Ｇａ Ｉ ｎＡｓ層と記す）２３、ｎ型不純
物が添加されたＡｌＩｎＡｓｌＩｎＡｓ層形４されてい
る。制御電極２６は、ｎ型ＡｕＩｎＡｓ層２４上に設け
られており、該制御電極２６０両側にソース電極２７お
よびドレイン電極２８が設けられている。On the InP substrate 21, an aluminum-indium-arsenic mixed crystal semiconductor layer (hereinafter referred to as an AaInAs layer) 22 and a gallium-indium-arsenic mixed crystal semiconductor layer (hereinafter referred to as a GaInAs layer) are formed on the InP substrate 21. 23, an AlInAslInAs layer 4 doped with n-type impurities. The control electrode 26 is provided on the n-type AuInAs layer 24, and a source electrode 27 and a drain electrode 28 are provided on both sides of the control electrode 260.
Ｇ ａ’ Ｉ ｎ Ａ ｓ層２３とｎ型ＡｌｌＩｎＡｓ
層２４の界面には、２次元電子層２５が形成されており
、この２次元電子層２５の電子密度を制御することによ
り、ソース電極２７とドレイン電極２８の間を流れる電
流が制御される。Ga'InAs layer 23 and n-type AllInAs
A two-dimensional electronic layer 25 is formed at the interface of the layer 24, and by controlling the electron density of the two-dimensional electronic layer 25, the current flowing between the source electrode 27 and the drain electrode 28 is controlled.
［発明が解決しようとする問題点コ
しかしながら、以上説明したような従来の電界効果トラ
ンジスタにおいては、意図的には不純物の添加されてい
ないＡ店ＩｎＡｓ層２２中にＩｎＰ基板２１中の不純物
が拡散し、得られたトランジスタの特性として、良好な
ピンチオフが得られないという問題点があった。また、
このように基板中の不純物により影響を受けるため、ト
ランジスタ特性が基板のロフトによってばらつきを生じ
るという問題点もあった。[Problems to be Solved by the Invention] However, in the conventional field effect transistor as described above, impurities in the InP substrate 21 are intentionally diffused into the A-store InAs layer 22 to which impurities are not added. However, the resulting transistor had a problem in that good pinch-off could not be obtained. Also,
Since the transistor characteristics are affected by impurities in the substrate, there is also a problem in that the transistor characteristics vary depending on the loft of the substrate.
それゆえに、本発明の目的は、ピンチオフ特性が優れ、
かつ基板のロットごとにばらつくことのない高品質の電
界効果トランジスタを提供することにある。Therefore, an object of the present invention is to have excellent pinch-off characteristics,
Another object of the present invention is to provide a high-quality field effect transistor that does not vary from substrate lot to lot.
「問題点を解決するための手段および作用］上記の目的
を達成するための本発明の構成を、実施例に対応する第
１図を用いて説明する。ＩｎＰ基板１上に、ｎ型不純物
が添加された第１のＡＩ Ｉ ｎ Ａ ｓ層２が形成さ
れ、該第１のＡＩＩｎＡＳ層２」二には、不純物が添加
されていないＧａＩｎＡｓ層３が形成され、さらに該Ｇ
ａ Ｉ ｎＡｓＡｓ上に第２のＡｕｌｎＡｓ層５か形成
される。第１のＡＣｊＩｎＡｓ層２には、ＩｎＰ基板１
から拡散する不純物の濃度に比べて非常に高い濃度のｎ
型不純物が添加される。"Means and operations for solving the problems" The structure of the present invention for achieving the above object will be explained using FIG. 1 corresponding to the embodiment. A first doped AIInAs layer 2 is formed, a GaInAs layer 3 to which no impurity is added is formed on the first AIInAS layer 2'', and further the GaInAs layer 3 is formed with no impurities added.
A second AlnAs layer 5 is formed on the a I nAsAs. The first ACjInAs layer 2 includes an InP substrate 1
The concentration of n is very high compared to the concentration of impurities diffused from
Type impurities are added.
以上の構成にすることにより、２次元電子層４は、第１
のＡ（ｊＩｎＡｓ層２とＧａＩｎＡｓ層３との間の界面
に形成され、従来と異なり基板に近い側に形成される。With the above configuration, the two-dimensional electronic layer 4
A (j is formed at the interface between the InAs layer 2 and the GaInAs layer 3, and unlike the conventional method, it is formed on the side closer to the substrate.
しかし、Ｇａ Ｉ ｎＡｓ層には、一般的にショットキ
ー接触を形成させることか難しい。そこで、本発明では
、Ｇａ ＩｎＡｓｎＡｓ層側上電極を直接形成させるの
ではなく、ショットキー接触を形成させることが容易な
材料をその上に形成した後、制御電極を形成させている
。このショットキー接触を形成させることが容易な材料
としてはＡｌＩｎＡｓが知られており、この理由から、
本発明において第２のＡαＩｎＡｓ層が形成されている
。第１図に示すように、第２のＡｌＩｎＡｓ層５上に制
御電極６を設けるこにより、制御電極６から空乏層が拡
がり、２次元電子層４の電子密度を制御することが可能
となり、これによってソース電極７とドレイン電極８の
間を流れる電流を制御することができる。However, it is generally difficult to form Schottky contacts in GaInAs layers. Therefore, in the present invention, instead of directly forming the upper electrode on the Ga InAsnAs layer side, a material with which a Schottky contact can be easily formed is formed thereon, and then the control electrode is formed. AlInAs is known as a material with which this Schottky contact can be easily formed, and for this reason,
In the present invention, a second AαInAs layer is formed. As shown in FIG. 1, by providing the control electrode 6 on the second AlInAs layer 5, a depletion layer expands from the control electrode 6, making it possible to control the electron density of the two-dimensional electron layer 4. Therefore, the current flowing between the source electrode 7 and the drain electrode 8 can be controlled.
また、本発明では、ＩｎＰ基板１上に、不純物濃度の高
いｎ型の第１のＡαＩｎＡｓ層が形成されているため、
ＩｎＰ基板１から拡散する不純物による影響を該第１の
ＡｆＬＩｎＡｓ層によって少なくすることができる。Furthermore, in the present invention, since the n-type first AαInAs layer with high impurity concentration is formed on the InP substrate 1,
The influence of impurities diffused from the InP substrate 1 can be reduced by the first AfLInAs layer.
［実施例］ 以下、本発明の一実施例を第１図に基づいて説明する。[Example] An embodiment of the present invention will be described below with reference to FIG.
半絶縁性ＩｎＰ基板１上に、有機金属気相成長法あるい
はガスソースＭ Ｂ Ｅ （Ｍｏｌｅｃｕｌａｒ−ｂｃ
ａｍ ｃｐｉｔａｘｙ）法により、基板温度６００’Ｃ
〜６５０℃において、ｎ型不純物を添加した第１のＡｌ
ｌｎＡｓ層２を形成する。ｎ型不純物としては、Ｓｉ、
Ｓ、Ｓｅなどを水素化物の形で供給し、その密度はｌＸ
ｌ０” 〜５ｘｌ ０１８ｃｍ−３程度にし、厚さは５
００Ａ〜２０００Ａの範囲にする。一般に、ＩｎＰ基板
１から拡散する不純物の密度は、１０”ｃｍ−３程度で
あり、また拡散深さも３００Ａ程度であるので、第１の
ＡＩ）、ＩｎＡｓｎＡｓ層上述の不純物密度および厚さ
とすることにより、ＩｎＰ基板１から拡散する不純物の
影響をほとんどなくすることができる。次に、不純物無
添加のＧａｌｎＡｓ層３を２００Ａ〜２０００人程度の
厚さで形成し、第２のＡαＩ’ｎＡｓ層５を２００Ａ〜
１００ＯＡ程度の厚さで形成する。第１のＡｒＬｌｎＡ
ｓ層２、ＧａＩｎＡｓ層３および第２のＡｌＩｎＡｓ層
５の混晶組成は、ＩｎＰ基板１との格子不整が０．１％
以下となるように形成する。On the semi-insulating InP substrate 1, organic metal vapor phase epitaxy or gas source MBE (Molecular-bc) is applied.
am cpitaxy) method, the substrate temperature is 600'C.
At ~650°C, the first Al doped with n-type impurities
An lnAs layer 2 is formed. As n-type impurities, Si,
S, Se, etc. are supplied in the form of hydrides, whose density is lX
10” to 5xl 018cm-3, and the thickness is 5
Set it in the range of 00A to 2000A. Generally, the density of impurities diffused from the InP substrate 1 is about 10"cm-3, and the diffusion depth is also about 300A. , it is possible to almost eliminate the influence of impurities diffused from the InP substrate 1.Next, an impurity-free GalnAs layer 3 is formed to a thickness of about 200A to 2000A, and a second AαI'nAs layer 5 is formed. 200A~
It is formed to a thickness of about 100 OA. First ArLlnA
The mixed crystal composition of the s-layer 2, the GaInAs layer 3, and the second AlInAs layer 5 has a lattice mismatch with the InP substrate 1 of 0.1%.
Form it as follows.
第２のＡＩＬＩｎＡｓ層５は、トランジスタの所要特性
により、不純物無添加、ｐ型またはｎ型にする。すなわ
ち、高入力耐圧が必要な場合には、不純物無添加とし、
高ドレイン電流が必要な場合にはｎ型とし、しきい値電
圧を正にする場合にはｐ型とする。ｎ型はＳｉ、Ｓ、Ｓ
ｅなどの不純物を１０” ｃｍ−３〜１０” ｃｍ−”
添加し、ｐ型はＺｎ、Ｍｇ、Ｍｎなどの不純物を１０１
１０ｌ６ ” 〜１０” ｃｍ−’程度添加する。The second AILInAs layer 5 is doped with no impurities and is made p-type or n-type depending on the required characteristics of the transistor. In other words, if high input withstand voltage is required, no impurities should be added.
When a high drain current is required, the n-type is used, and when the threshold voltage is positive, the p-type is used. n-type is Si, S, S
impurities such as 10" cm-3 to 10"cm-"
For p-type, impurities such as Zn, Mg, and Mn are added to 101
Add approximately 10l6'' to 10''cm-'.
さらにＡｕ−Ｇｅ合金からなる低抗性接触金属を蒸着し
、たとえば４００°Ｃで合金化することにより、ソース
電極７およびドレイン電極８を形成する。最後に、たと
えばＡ肛、 Ｐ ｔ、 Ａｕ、 Ｗ。Further, a low resistance contact metal made of an Au-Ge alloy is deposited and alloyed at, for example, 400°C to form the source electrode 7 and the drain electrode 8. Finally, for example, A anal, P t, Au, W.
ＷＳｉなどから選ばれた制御電極６を蒸芒法などの方法
により形成し完成させる。A control electrode 6 made of WSi or the like is formed and completed by a method such as a steaming method.
［発明の効果コ
本発明の電界効果トランジスタでは、ＩｎＰ基板上に意
図的に高濃度のｎ型不純物を添加した第１のＡ仁１ｎＡ
ｓ層が形成されているため、ＩｎＰ基板から拡散する不
純物の影響を著しく低減させることができる。したがで
て、本発明によれば、再現性良く、高周波特性・増幅特
性の優れた電界効果トランジスタとすることができる。[Effects of the Invention] In the field effect transistor of the present invention, the first A layer 1nA is intentionally doped with a high concentration of n-type impurity on the InP substrate.
Since the s-layer is formed, the influence of impurities diffused from the InP substrate can be significantly reduced. However, according to the present invention, a field effect transistor with good reproducibility and excellent high frequency characteristics and amplification characteristics can be obtained.
第１図は、本発明の一実施例を説明するための断面図で
ある。第２図は、従来の電界効果トランジスタを示す断
面図である。
図において、１はＩｎＰ基板、２は第１のＡＣ７ｎＡｓ
層、３はＧａ Ｉ ｎＡｓ層、４は２次元電子層、５は
第２のＡＱｌｎＡｓ層、６は制御電極、７はソース電極
、８はドレイン電極を示す。
（ほか２名） ゛、’、、Ｈ−＋
第２図
２７２ど ２３FIG. 1 is a sectional view for explaining one embodiment of the present invention. FIG. 2 is a sectional view showing a conventional field effect transistor. In the figure, 1 is an InP substrate, 2 is a first AC7nAs
3 is a GaInAs layer, 4 is a two-dimensional electronic layer, 5 is a second AQlnAs layer, 6 is a control electrode, 7 is a source electrode, and 8 is a drain electrode. (2 others) ゛,',,H-+ Figure 2 272 etc. 23
Claims (4)
ＡｌＩｎＡｓ層を形成し、該第１のＡｌＩｎＡｓ層上に
不純物が添加されていないＧａＩｎＡｓ層を形成し、該
ＧａＩｎＡｓ層上に第２のＡｌＩｎＡｓ層を形成し、該
第２のＡｌＩｎＡｓ層上に制御電極を設け、該制御電極
の両側に前記ＧａＩｎＡｓ層に対して抵抗性接触となる
ソース電極およびドレイン電極を設けたことを特徴とす
る、電界効果トランジスタ。(1) A first AlInAs layer doped with an n-type impurity is formed on an InP substrate, a GaInAs layer to which no impurity is added is formed on the first AlInAs layer, and a second AlInAs layer is formed on the GaInAs layer. A second AlInAs layer is formed, a control electrode is provided on the second AlInAs layer, and a source electrode and a drain electrode that are in resistive contact with the GaInAs layer are provided on both sides of the control electrode. field effect transistor.
いないことを特徴とする特許請求の範囲第１項記載の電
界効果トランジスタ。(2) The field effect transistor according to claim 1, wherein no impurity is added to the second AlInAs layer.
ことを特徴とする、特許請求の範囲第１項記載の電界効
果トランジスタ。(3) The field effect transistor according to claim 1, wherein the conductivity type of the second AlInAs layer is p-type.
ことを特徴とする、特許請求の範囲第１項記載の電界効
果トランジスタ。(4) The field effect transistor according to claim 1, wherein the conductivity type of the second AlInAs layer is n-type.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25418186A JPS63107173A (en) | 1986-10-24 | 1986-10-24 | Field effect transistor |
| EP87115444A EP0264932A1 (en) | 1986-10-24 | 1987-10-21 | Field effect transistor |
| CA000550121A CA1261977A (en) | 1986-10-24 | 1987-10-23 | Field effect transistor |
| KR1019870011772A KR900008154B1 (en) | 1986-10-24 | 1987-10-23 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25418186A JPS63107173A (en) | 1986-10-24 | 1986-10-24 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63107173A true JPS63107173A (en) | 1988-05-12 |
| JPH0312770B2 JPH0312770B2 (en) | 1991-02-21 |
Family
ID=17261356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25418186A Granted JPS63107173A (en) | 1986-10-24 | 1986-10-24 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63107173A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0230149A (en) * | 1988-07-20 | 1990-01-31 | Sanyo Electric Co Ltd | Hetero junction field effect transistor |
| US5127603A (en) * | 1989-12-13 | 1992-07-07 | Shimano Industrial Co., Ltd. | Fishing reel with cover for enclosing control dial |
-
1986
- 1986-10-24 JP JP25418186A patent/JPS63107173A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0230149A (en) * | 1988-07-20 | 1990-01-31 | Sanyo Electric Co Ltd | Hetero junction field effect transistor |
| US5127603A (en) * | 1989-12-13 | 1992-07-07 | Shimano Industrial Co., Ltd. | Fishing reel with cover for enclosing control dial |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0312770B2 (en) | 1991-02-21 |
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