JPS63107061A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To eliminate completely a leak current between transistors of neigh bouring cells, and control the malfunction due to interference between the cells, by forming a transistor of TTC structure in the inside of a groove, and separat ing completely a transistor from a silicon substrate. CONSTITUTION:On a semiconductor substrate 1, an insulative film 2 is formed, this insulative film 2 is subjected to patterning in the form of a groove, a groove 4 is formed on the semiconductor substrate 1 by applying the film to a mask, a capacitor insulative film 5 is formed on the insidewall of the groove 4, and capacitor electrodes 6 and 7 are burried. Further, a gate electrode material is formed on the insidewall of the groove 4, and at least a part 13 of the capaci tor electrodes 6 and 7 is crystallized, and from this part a channel region 4 is formed by epitaxial growth. Then, a bit wire 15 connecting to the channel region 4 is formed. For example, after a gate oxide film 11 is formed, a surface 13 of the capacitor electrodes 6 and 7 is recrystallized by electron beam annealing or laser beam annealing, and a silicon film 14 which serves as the channel region of a transistor is formed by epitaxial growth applying the recrys tallized part as a seed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device having a one-transistor/one-capacitor memory cell structure that stores information using charges accumulated in a capacitor. (2) Concerning the manufacturing method.

(Prior Art) In general, a dynamic RAM (dRAM) memory cell consists of a MOS capacitor that holds information in the form of charge, and a switching MOS capacitor that exchanges the charge with an external circuit.
It is composed of OS transistors. As the capacity of dRAH continues to increase, the area occupied by one memory cell is inevitably decreasing; for example, 16 Mbit
In dRAH, the cell area is predicted to be several -2. In order to form a capacitor large enough to carry sufficient information charge in such a small area and a MOS transistor that performs proper switching operations, we have recently dug trenches in the semiconductor substrate and placed capacitors and transistors on the inner surface of the trenches. A method for forming a TTC (Trench Transistor Cell) was proposed by Texas Instruments (see FIG. 4). This cell structure is called a cross-point cell structure, in which the entire capacitor and transistor is built into a trench located at the intersection of a word line and a bit line.

This structure is considered to be a promising form of research for high integration.

However, when this cell structure is miniaturized, the capacitors of adjacent cells are completely separated and there is no problem, but as shown in FIG. Contact (b
(uried contact) Between 17 comrades, Si
They are close to each other through the substrate and interfere with each other due to leakage current, and information and operations of neighboring cells cause malfunctions of the cells. Therefore, currently,
Form the element valve wi region 2, channel 18 comrades and bu
ried contact 17 I have enough information from my comrades, but it is 113Mbit or more. 1! When considering integration, this interference becomes an obstacle to miniaturization.

(Problems to be Solved by the Invention) As described above, in TTC @ construction, the transistors of adjacent cells are not completely separated, so it is necessary to maintain a sufficient distance between the cells to prevent interference. There was a problem that this became an obstacle to miniaturization.

An object of the present invention is to provide a method for manufacturing a semiconductor memory device that solves these problems.

(Structure of the Invention) (Means for Solving the Problems) In order to achieve the above objects, the present invention provides TTC
The structure is characterized in that the transistor is formed inside the trench, and the transistor and the silicon substrate are completely separated.

(Function) According to the method of the present invention, a transistor with a TTC structure is formed inside a trench and is completely separated from the transistor and contact of an adjacent cell through an insulating film. Completely eliminates leakage current,
It becomes possible to suppress malfunctions due to interference between cells.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
Figures @~0) are cross-sectional views showing the manufacturing process of one embodiment. FIG. 2 shows a finished top view. FIG. 3 shows a finished sectional view along line segment 8B' in FIG. As shown in FIG. 1(2), the entire surface of the highly doped p-type 3i substrate 1 is
A silicon oxide film 2 of about 1 μm is formed by thermal oxidation or CVD, and a resist 3 is applied thereon and patterned.

Using this as a mask, grooves 4 are formed by reactive ion etching to a depth of several inches from the surface of the silicon substrate.

Next, as shown in FIG. 1, silicon oxide 1115 is formed as a capacitor oxide film by thermal oxidation.

Next, as shown in FIG. 1(C), a phosphorus-doped polycrystalline silicon film 6 and a non-doped polycrystalline silicon film 7, which will become capacitor electrodes, are deposited on the entire surface, and as shown in FIG. Etch to depth using reactive ion etching to form capacitor electrodes.

Next, as shown in FIG. 1(e), silicon oxide films 8 and 9 are formed by thermal oxidation to separate and insulate the capacitor electrode and the gate electrode of the transistor, and then the phosphorus-doped polycrystalline silicon of the gate material is formed. A film 10 is deposited on the entire surface by the CVD method, and polycrystalline silicon is etched only on the inner wall of the trench 4 by reactive ion etching as shown in FIG.
O' is left as a gate electrode.

Next, a silicon oxide film 11 which will become a gate oxide film is formed by a thermal oxidation method (see ω in FIG. 1). Next, after removing the silicon oxide film 12 on the capacitor electrodes 6 and 7 by reactive ion etching, the surface 13 of the capacitor electrode is recrystallized by electron beam annealing or laser annealing as shown in FIG. become Using this part as a seed, the silicon ll11 becomes the channel region of the transistor.
4 to grow shrimp (see Figure 1 (υ)).

Next, in order to make the interlayer insulating film between the bit line and the gate sufficiently thick, thermal oxidation is performed to thicken the silicon oxide film 11.
A silicon oxide film 11' is formed, and the thin silicon oxide film 11' formed on the shrimp film 14 is removed by etching in order to make contact with the bit line (see Figure 1).
.

Next, a phosphorus-doped polycrystalline silicon film 15 is deposited over the entire surface, and an n-type diffusion layer 16 is formed by making direct contact with the epitaxial layer 114. The process is completed by patterning the bit lines. The transistor will be connected to bit line 15 via diffusion 1116.

The gate electrode 10' of each cell is formed by etching the silicon oxide film 2 between the trenches 4 before the process shown in FIG. Crystalline silicon film 10″ (see Figures 2 and 3),
are connected to form a word line.

〔Effect of the invention〕

According to the present invention, in a cross-point cell structure, the capacitor electrode and transistor of each cell are formed inside the groove, and the insulating film is formed around the cell, so that adjacent cells are completely isolated from each other. separated into A highly integrated cell structure with very stable operation that is completely free from disturbances from adjacent cells due to leakage current and coupling becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of an embodiment of the present invention, FIG. 2 is a top view of a cell obtained by an embodiment of the present invention, and FIG. 3 is a cross section taken in a direction perpendicular to FIG. 1. (a sectional view taken along line segment AA' in FIG. 2) and FIG. 4 are sectional views showing a conventional example. 1...High concentration p-type S1 substrate 2...Silicon oxide film 3...Resist 4...
Groove 5...Silicon oxide film 6...Phosphorus-doped polycrystalline silicon film 7...Non-doped polycrystalline silicon film 8...Silicon oxide film 9...Silicon oxide film 1
0, 10', 10''...polycrystalline silicon film 11,
11', 11''...Silicon oxide film 12...Silicon oxide 'I!A13...Recrystallized region 14...
Shrimp-grown silicon film 15...Phosphorus-doped polycrystalline silicon film 16...N-type diffusion layer 17...Buried contact 18...Vertical transistor channel region 19...Diffusion layer agent Patent attorney Nori Chika Ken Yudo Takehana Kikuo Figure 1

Claims (1)

[Claims] A process of forming an insulating film on a semiconductor substrate, patterning the insulating film into a groove shape, forming a groove in the semiconductor substrate using this as a mask, forming a capacitor insulating film on the inner wall of the groove, and forming a capacitor electrode. further forming a gate electrode material on the inner wall of the trench; crystallizing at least a portion of the capacitor electrode and forming a channel region from this region by epitaxial growth;
A method of manufacturing a semiconductor memory device, comprising the step of forming a bit line connected to the channel region.