JPS63107001U - - Google Patents
Info
- Publication number
- JPS63107001U JPS63107001U JP20414286U JP20414286U JPS63107001U JP S63107001 U JPS63107001 U JP S63107001U JP 20414286 U JP20414286 U JP 20414286U JP 20414286 U JP20414286 U JP 20414286U JP S63107001 U JPS63107001 U JP S63107001U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- differential amplifier
- input terminal
- terminal connected
- amplifier circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 230000010355 oscillation Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Feedback Control In General (AREA)
Description
第１図は本考案の一実施例を示す電気回路図、
第２図は第１図の作動説明図、第３図は従来例を
示す電気回路図である。 １……基準電圧設定回路、２……電圧比較器、
６……差動増幅回路、７……発振回路、８……検
出回路。
第２図は第１図の作動説明図、第３図は従来例を
示す電気回路図である。 １……基準電圧設定回路、２……電圧比較器、
６……差動増幅回路、７……発振回路、８……検
出回路。
Claims (1)
- 検出回路と基準電圧設定回路とが入力端に接続
された差動増幅回路と、当該差動増幅回路の出力
端と発振回路とが入力端に接続された電圧比較器
とを備えたことを特徴とするフイードバツク制御
回路。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20414286U JPS63107001U (ja) | 1986-12-26 | 1986-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20414286U JPS63107001U (ja) | 1986-12-26 | 1986-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63107001U true JPS63107001U (ja) | 1988-07-11 |
Family
ID=31170122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20414286U Pending JPS63107001U (ja) | 1986-12-26 | 1986-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63107001U (ja) |
-
1986
- 1986-12-26 JP JP20414286U patent/JPS63107001U/ja active Pending