JPS63106219U - - Google Patents

Info

Publication number
JPS63106219U
JPS63106219U JP20376086U JP20376086U JPS63106219U JP S63106219 U JPS63106219 U JP S63106219U JP 20376086 U JP20376086 U JP 20376086U JP 20376086 U JP20376086 U JP 20376086U JP S63106219 U JPS63106219 U JP S63106219U
Authority
JP
Japan
Prior art keywords
gate
semiconductor device
input terminal
delay circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20376086U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20376086U priority Critical patent/JPS63106219U/ja
Publication of JPS63106219U publication Critical patent/JPS63106219U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP20376086U 1986-12-25 1986-12-25 Pending JPS63106219U (bs)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20376086U JPS63106219U (bs) 1986-12-25 1986-12-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20376086U JPS63106219U (bs) 1986-12-25 1986-12-25

Publications (1)

Publication Number Publication Date
JPS63106219U true JPS63106219U (bs) 1988-07-09

Family

ID=31169390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20376086U Pending JPS63106219U (bs) 1986-12-25 1986-12-25

Country Status (1)

Country Link
JP (1) JPS63106219U (bs)

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