JPS6310557U - - Google Patents

Info

Publication number
JPS6310557U
JPS6310557U JP10462486U JP10462486U JPS6310557U JP S6310557 U JPS6310557 U JP S6310557U JP 10462486 U JP10462486 U JP 10462486U JP 10462486 U JP10462486 U JP 10462486U JP S6310557 U JPS6310557 U JP S6310557U
Authority
JP
Japan
Prior art keywords
layer
silicon
conductive layer
silicon layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10462486U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10462486U priority Critical patent/JPS6310557U/ja
Publication of JPS6310557U publication Critical patent/JPS6310557U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す半導体装置の
断面図である。第2図は従来のLSIチツプ表面
のGNDラインの形状例を示す斜視図である。 3……シリコン基板、4……接地導電層、5…
…絶縁層、6……SOI技術によるシリコン層、
7……貫通導電層、8……SiO層、9……半
導体素子、11……接地電極。
FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention. FIG. 2 is a perspective view showing an example of the shape of a GND line on the surface of a conventional LSI chip. 3...Silicon substrate, 4...Ground conductive layer, 5...
...Insulating layer, 6...Silicon layer by SOI technology,
7... Penetrating conductive layer, 8... SiO 2 layer, 9... Semiconductor element, 11... Ground electrode.

Claims (1)

【実用新案登録請求の範囲】 シリコン基板の上に、順に積層された接地導電
層、絶縁層、SOI〔シリコン・オン・インシユ
レータ〕技術により形成されたシリコン層と、 上記シリコン層に形成されたアクテイブ領域及
びフイールド領域と、 上記接地導電層から上記絶縁層及びシリコン層
を貫通してシリコン層上の接地電極にまで延びる
貫通導電層とを有することを特徴とする半導体装
置。
[Claims for Utility Model Registration] A grounded conductive layer, an insulating layer, a silicon layer formed by SOI (silicon on insulator) technology, and an active layer formed on the silicon layer, which are laminated in this order on a silicon substrate. What is claimed is: 1. A semiconductor device comprising: a region and a field region; and a through conductive layer extending from the ground conductive layer through the insulating layer and the silicon layer to a ground electrode on the silicon layer.
JP10462486U 1986-07-08 1986-07-08 Pending JPS6310557U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10462486U JPS6310557U (en) 1986-07-08 1986-07-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10462486U JPS6310557U (en) 1986-07-08 1986-07-08

Publications (1)

Publication Number Publication Date
JPS6310557U true JPS6310557U (en) 1988-01-23

Family

ID=30978290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10462486U Pending JPS6310557U (en) 1986-07-08 1986-07-08

Country Status (1)

Country Link
JP (1) JPS6310557U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5513947A (en) * 1978-07-17 1980-01-31 Seiko Epson Corp Semiconductor integrated circuit device
JPS59115555A (en) * 1982-12-22 1984-07-04 Toshiba Corp Semiconductor integrated circuit
JPS60210860A (en) * 1984-04-04 1985-10-23 Sharp Corp Semiconductor ic element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5513947A (en) * 1978-07-17 1980-01-31 Seiko Epson Corp Semiconductor integrated circuit device
JPS59115555A (en) * 1982-12-22 1984-07-04 Toshiba Corp Semiconductor integrated circuit
JPS60210860A (en) * 1984-04-04 1985-10-23 Sharp Corp Semiconductor ic element

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