JPS63105535A - Duplex circuit system - Google Patents

Duplex circuit system

Info

Publication number
JPS63105535A
JPS63105535A JP25254286A JP25254286A JPS63105535A JP S63105535 A JPS63105535 A JP S63105535A JP 25254286 A JP25254286 A JP 25254286A JP 25254286 A JP25254286 A JP 25254286A JP S63105535 A JPS63105535 A JP S63105535A
Authority
JP
Japan
Prior art keywords
signal
switching
circuit
output
state buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25254286A
Other languages
Japanese (ja)
Inventor
Yoshitaka Kato
加藤 良孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25254286A priority Critical patent/JPS63105535A/en
Publication of JPS63105535A publication Critical patent/JPS63105535A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To decrease the number of lines required for confounding paths by inserting a tri-state buffer to the confounding path in a changeover means confounding an active system and a standby system. CONSTITUTION:The tri-state buffers 10, 11 in the active system 1 and the standby system 2 are connected respectively to the sending end of pre-stage circuits 3, 4 each and controlled by a switching control signal 7. Outputs of the tri-state buffers 10, 11 are connected multiply and given to switching circuits 8, 9 respectively via a path 12, where a signal flows bidirectionally. Then the output of the tri-state buffer 10 of the active side is enabled when the switching circuits 8, 9 select and pass the signal from the pre-stage circuit 3 of the active system in the tri-state buffers 10, 11 and the output of the tri-state buffer 11 of the standby system is brought into a high impedance. In this case, the bidirectional confounding path 12 is connected from the active to the standby system.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、通信機器の現用、予備の切替手段に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to active/backup switching means for communication equipment.

〔概要〕〔overview〕

本発明は、現用、予備の二重化構成で現用系と予備系の
交絡をとる切替手段において、3ステートバフフアを交
絡経路に挿入することにより、 交絡経路が所要とする線路の数量を少なくすることがで
きるようにしたものである。
The present invention reduces the number of lines required by the confounding path by inserting a 3-state buffer into the confounding path in a switching means that removes the confounding of the working system and the backup system in a duplex configuration of the working system and the backup system. It was made so that it could be done.

〔従来の技術〕[Conventional technology]

従来のこの種の切替方式の構成の一例を第2図に示す。 An example of the configuration of a conventional switching system of this type is shown in FIG.

この従来例方式は、現用系14および予備系15の各々
の前段回路16および17と、後段回路18および19
と、この前段回路16および17と後段回路18および
19との間に挿入され、各々前段回路16および17か
らの出力信号と交絡を取った相手の出力信号とを入力し
、切替制御信号20により正常な系に切替および切戻し
を行う切替回路21および22と、現用系14と予備系
15の前段回路16および17からの障害情報に基づき
切替制御信号20を各々の切替回路21および22に発
出する切替制御信号発生回路23とから構成されていた
This conventional system includes front-stage circuits 16 and 17 and rear-stage circuits 18 and 19 of each of the active system 14 and the backup system 15.
It is inserted between the front stage circuits 16 and 17 and the rear stage circuits 18 and 19, and inputs the output signals from the front stage circuits 16 and 17 and the output signal of the other party which has been deconfounded. A switching control signal 20 is issued to each switching circuit 21 and 22 based on fault information from the switching circuits 21 and 22 that switch to and return to the normal system, and the front stage circuits 16 and 17 of the active system 14 and standby system 15. The switching control signal generating circuit 23 was configured to perform the following steps.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このような従来例切替手段では、現用系から予備系へ、
および予備系から現用系への信号の経路を個別に設ける
必要があるので、切替を必要とする信号線の数が多い装
置では、交絡を実現するケーブルの量が装置の構成上大
きな負担になる欠点がある。
In such conventional switching means, from the active system to the standby system,
In addition, it is necessary to provide separate signal paths from the backup system to the active system, so in equipment with a large number of signal lines that require switching, the amount of cables required to achieve interlacing becomes a major burden on the equipment configuration. There are drawbacks.

本発明はこのような欠点を除去するもので、交絡を実現
するケーブル量を節減することができる二重化回路方式
を提供することを目的とする。
The present invention aims to eliminate such drawbacks and to provide a duplex circuit system that can reduce the amount of cables required for interlacing.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、第一の信号を送出する第一信号回路と、この
第一の信号に等しい第二の信号を送出する第二信号回路
と、第一および第二の信号を入力し、いずれか一方を選
択する第一切替回路および第二切替回路と、上記第一お
よび第二切替回路に切替制御信号を与える制御回路とを
備えた二重化回路方式において、第一の信号を入力し、
切替制御信号でそのインピーダンスが制御され、出力を
上記切替回路の一方に与える第一の3ステートバッファ
と、第二の信号を入力し、切替制御信号でそのインピー
ダンスが制御され、出力を上記切替回路の他方に与える
第二の3ステートバッファと、上記切替回路の一方に第
一の信号を与える第一の電路と、上記切替回路の他方に
第二の信号を与える第二の電路と、上記第一の3ステー
トバッファの出力と上記第二の3ステートバッファの出
力とを交絡する第三の電路とを備えたことを特徴とする
The present invention provides a first signal circuit that sends out a first signal, a second signal circuit that sends out a second signal equal to the first signal, and a first signal circuit that receives the first and second signals. In a duplex circuit system comprising a first switching circuit and a second switching circuit that select one of the switching circuits, and a control circuit that provides a switching control signal to the first and second switching circuits, inputting the first signal,
A first 3-state buffer whose impedance is controlled by a switching control signal and provides an output to one of the switching circuits, and a second signal is input to which the impedance is controlled by the switching control signal and the output is sent to the switching circuit. a second three-state buffer that provides a first signal to one of the switching circuits; a second electrical path that provides a second signal to the other switching circuit; The present invention is characterized by comprising a third electric path that intertwines the output of the first three-state buffer and the output of the second three-state buffer.

〔作用〕[Effect]

平常は、第一信号回路の出力は第一切替回路を経由し、
また第二信号回路の出力は第二切替回路を経由するもの
とすると、第一信号回路が障害状態になると、第二信号
回路にかかわる3ステートバッファはローインピーダン
スになり、第二信号回路の出力はこの3ステートバッフ
ァを経由して第一切替回路に到る。このときに、第一信
号回路にかかわる3ステートバッファはハイインピーダ
ンスに制御されて信号の通過を許さない。すなわち、二
つの切替回路を経由する信号は第二信号回路の出力であ
る。
Normally, the output of the first signal circuit goes through the first switching circuit,
Also, assuming that the output of the second signal circuit passes through the second switching circuit, when the first signal circuit becomes in a fault state, the 3-state buffer related to the second signal circuit becomes low impedance, and the output of the second signal circuit reaches the first switching circuit via this three-state buffer. At this time, the three-state buffer associated with the first signal circuit is controlled to be high impedance and does not allow any signal to pass through. That is, the signals passing through the two switching circuits are the outputs of the second signal circuit.

〔実施例〕〔Example〕

以下、本発明の一実施例を図面に基づいて説明する。 Hereinafter, one embodiment of the present invention will be described based on the drawings.

第1図はこの実施例の構成を示すブロック構成図である
FIG. 1 is a block diagram showing the configuration of this embodiment.

まず、この実施例の構成を第1図に基づき説明する。こ
の実施例は現用系1と、予備系2と、切替制御信号発生
回路13とを備え、ここで、現用系1は、前段回路3と
、後段回路5と、切替回路8と、3ステートバッファ1
0とを備え、また、予備系2は、前段回路4と、後段回
路6と、切替回路9と3ステートバッファ11とを備え
る。
First, the configuration of this embodiment will be explained based on FIG. This embodiment includes an active system 1, a standby system 2, and a switching control signal generation circuit 13, where the active system 1 includes a front-stage circuit 3, a rear-stage circuit 5, a switching circuit 8, and a three-state buffer. 1
Further, the standby system 2 includes a front-stage circuit 4, a rear-stage circuit 6, a switching circuit 9, and a three-state buffer 11.

次に、この実施例の動作を第1図に基づき説明する。Next, the operation of this embodiment will be explained based on FIG.

切替回路8および9は現用系1および予備系2の各々の
前段回路3および4と後段回路5および6との間に挿入
され、各々の前段回路3および4からの出力信号と交絡
を取った相手の系の出力信号とを入力し、切替制御信号
7に基づき正常な系に切替および切戻しを行う。3ステ
ートバッファ10および11は、各々の前段回路3およ
び4がらの送信端に接続され、切替制御信号7で制御さ
れる。
Switching circuits 8 and 9 are inserted between the front stage circuits 3 and 4 and the rear stage circuits 5 and 6 of each of the active system 1 and the backup system 2, and remove confounds with the output signals from the respective front stage circuits 3 and 4. The system inputs the output signal of the other system, and switches to and returns to the normal system based on the switching control signal 7. The 3-state buffers 10 and 11 are connected to the transmitting ends of the respective front-stage circuits 3 and 4, and are controlled by the switching control signal 7.

各々の3ステートバッファ10および11の出力はマル
チ接続され、双方向に信号が流れる交絡の経路12を経
由して各々の切替回路8および9に入力する。切替制御
信号発生回路13は、前段回路3および4の障害情報を
収集し、切替側?H*号7を発出する。また、3ステー
トバッファ10および11は、切替回路8および9が現
用の前段回路3からの信号を選択し通過させている場合
は、現用側の3ステートバフフア10の出力を出力可能
状態とし、予備側の3ステートバッファ11の出力をハ
イインピーダンス状態にする。このときに双方向の交絡
の経路12は現用から予備に流れる0次に、切替回路8
および9が予備の前段回路4からの信号を選択し通過さ
せている場合は、予備側の3ステートバッファ11の出
力を出力可能状態とし、現用側の3ステートバッファ1
0の出力をハイインピーダンス状態にする。このときに
、双方向の交絡経路12は予備から現用に流れる。
The outputs of the respective three-state buffers 10 and 11 are multi-connected and input to the respective switching circuits 8 and 9 via intertwined paths 12 through which signals flow in both directions. The switching control signal generation circuit 13 collects fault information of the preceding stage circuits 3 and 4, and determines whether the switching side? Issue H* No. 7. In addition, when the switching circuits 8 and 9 select and pass the signal from the currently used previous stage circuit 3, the 3-state buffers 10 and 11 enable the output of the currently used 3-state buffer 10, The output of the 3-state buffer 11 on the standby side is brought into a high impedance state. At this time, the bidirectional intertwined path 12 is the 0th order flowing from the working to the standby, and the switching circuit 8
and 9 selects and passes the signal from the preliminary front stage circuit 4, the output of the 3-state buffer 11 on the auxiliary side is enabled for output, and the 3-state buffer 11 on the active side
0 output to high impedance state. At this time, the bidirectional intertwined path 12 flows from the standby to the active path.

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明したように、交絡の各々の送4#;端
に3ステートバッファを設けて、交絡の経路を双方向と
することができるので、従来の片方向の経路を両方向に
向けて設けていた場合に較べて信号線を2分の1に減少
することができる効果がある。
As explained above, in the present invention, a 3-state buffer is provided at each end of the confounding transmission, so that the confounding route can be made bidirectional. This has the effect of reducing the number of signal lines to one half compared to the case where the signal lines are provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例の構成を示すブロック構成図6 第2図は従来例の構成を示すブロック構成図。 1.14・・・現用系、2.15・・・予備系、3.4
.16.17−・・前段回路、5.6.18.19・・
・後段回路、7.20・・・切替制御信号、8.9.2
1.22・・・切替回路、10.11・・・3ステート
バフフア、12・・・交絡経路、13.23・・・切替
制御信号発生回路。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a conventional example. 1.14... Active system, 2.15... Backup system, 3.4
.. 16.17--Previous stage circuit, 5.6.18.19...
・Late stage circuit, 7.20...Switching control signal, 8.9.2
1.22... Switching circuit, 10.11... 3-state buffer, 12... Confounding path, 13.23... Switching control signal generation circuit.

Claims (1)

【特許請求の範囲】[Claims] (1)第一の信号を送出する第一信号回路(3)と、こ
の第一の信号に等しい第二の信号を送出する第二信号回
路(4)と、 第一および第二の信号を入力し、いずれか一方を選択す
る第一切替回路(8)および第二切替回路(9)と、 上記第一および第二切替回路に切替制御信号を与える制
御回路(13)と を備えた二重化回路方式において、 第一の信号を入力し、切替制御信号でそのインピーダン
スが制御され、出力を上記切替回路の一方に与える第一
の3ステートバッファ(10)と、第二の信号を入力し
、切替制御信号でそのインピーダンスが制御され、出力
を上記切替回路の他方に与える第二の3ステートバッフ
ァ(11)と、上記切替回路の一方に第一の信号を与え
る第一の電路(25)と、 上記切替回路の他方に第二の信号を与える第二の電路(
26)と、 上記第一の3ステートバッファの出力と上記第二の3ス
テートバッファの出力とを交絡する第三の電路(12)
と を備えたことを特徴とする二重化回路方式。
(1) A first signal circuit (3) that sends out a first signal, a second signal circuit (4) that sends out a second signal equal to this first signal, and a A duplex device comprising a first switching circuit (8) and a second switching circuit (9) for inputting the input signal and selecting one of them, and a control circuit (13) for giving a switching control signal to the first and second switching circuits. In the circuit system, a first 3-state buffer (10) is inputted with a first signal, the impedance of which is controlled by a switching control signal, and provides an output to one of the switching circuits, and a second signal is inputted; a second three-state buffer (11) whose impedance is controlled by a switching control signal and provides an output to the other of the switching circuits; a first electric line (25) that provides a first signal to one of the switching circuits; , a second electric line (
26), and a third electric path (12) that intertwines the output of the first 3-state buffer and the output of the second 3-state buffer.
A redundant circuit system characterized by the following.
JP25254286A 1986-10-22 1986-10-22 Duplex circuit system Pending JPS63105535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25254286A JPS63105535A (en) 1986-10-22 1986-10-22 Duplex circuit system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25254286A JPS63105535A (en) 1986-10-22 1986-10-22 Duplex circuit system

Publications (1)

Publication Number Publication Date
JPS63105535A true JPS63105535A (en) 1988-05-10

Family

ID=17238822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25254286A Pending JPS63105535A (en) 1986-10-22 1986-10-22 Duplex circuit system

Country Status (1)

Country Link
JP (1) JPS63105535A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10234107A (en) * 1996-11-19 1998-09-02 Hyundai Motor Co Method for sending speed command in electric vehicle and device therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10234107A (en) * 1996-11-19 1998-09-02 Hyundai Motor Co Method for sending speed command in electric vehicle and device therefor

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