JPS63102222A - Epitaxial growth method - Google Patents

Epitaxial growth method

Info

Publication number
JPS63102222A
JPS63102222A JP24750886A JP24750886A JPS63102222A JP S63102222 A JPS63102222 A JP S63102222A JP 24750886 A JP24750886 A JP 24750886A JP 24750886 A JP24750886 A JP 24750886A JP S63102222 A JPS63102222 A JP S63102222A
Authority
JP
Japan
Prior art keywords
growth
interface
temperature
grown
hetero
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24750886A
Other languages
Japanese (ja)
Inventor
Shigeya Narizuka
重弥 成塚
Yoshihiro Kokubu
国分 義弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24750886A priority Critical patent/JPS63102222A/en
Publication of JPS63102222A publication Critical patent/JPS63102222A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the flatness of the interface by bringing the growth temperature of a single crystal substrate to a specified temperature or less and interrupting epitaxial growth for a specific time or more on a hetero-interface when a III-V compound semiconductor crystal including the hetero-interface is grown in an epitaxial manner. CONSTITUTION:When a III-V compound semiconductor crystal containing a hetero- interface is grown in an epitaxial manner, the temperature of a single crystal substrate is kept at 650 deg.C or less, growth is interrupted for five min or more on the hetero- interface, and an epitaxial growth layer is formed. When a growth temperature is lowered to 650 deg.C or less, the size of irregular islands in a grown surface is brought to 300Angstrom or more. When epitaxial growth is suspended at that time, the irregular islands mutually couple in the grown surface to shape larger islands. Growth is interrupted for five min or more in order to promote the speed of mutual coupling of the islands. When arsine (AsH3), trimethylgallium (TMG) and trimethylaluminum (TMA) are employed as a raw material gas and applied to GaAs-AlGaAs quantum well structure, growth is suspended for five min before and after a well layer is grown. The temperature of the substrate is brought to 650 deg.C. A V/III ratio is brought to 200 and a growth rate to 1.8A/sec in GaAs.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明はヘテロ界面を含む■−■族化合物半導体結晶の
エピタキシャル成長方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention] (Industrial Application Field) The present invention relates to a method for epitaxial growth of a ■-■ group compound semiconductor crystal containing a heterointerface.

(従来の技術) 半導体素子の高性能化のため超格子構造の素子が注目さ
れている。このためには模写及び界面での組成変fヒの
急峻性や界面の平坦性の側聞が非常に重要である。
(Prior Art) Elements with superlattice structures are attracting attention in order to improve the performance of semiconductor elements. For this purpose, the steepness of the composition change at the copy and interface and the flatness of the interface are very important.

■−v族化合物半導体結晶のヘテロ界面平坦性向上のた
め、分子線エピタキシャル成長法では界面における成長
中断法が用いられているが、有機金属気相成長法では、
特別な方法は何ら報告されてdない。
■-In order to improve the flatness of the heterointerface of group V compound semiconductor crystals, growth interruption at the interface is used in molecular beam epitaxial growth, but in metal-organic vapor phase epitaxy,
No special method has been reported.

従来の有機金属気相成長法では、成長温度、V/■比、
成長速度等の成長パラメータt−最適に選んでもヘテロ
界面の平坦性向上におのずと限界がある。flえば、渡
辺他(The 2nd InζConf、 onMod
ulated Sem1conductor 8tru
ctures、Kyoto。
In conventional metal-organic vapor phase epitaxy, growth temperature, V/■ ratio,
Even if the growth parameter t, such as the growth rate, is optimally selected, there is naturally a limit to the improvement in the flatness of the heterointerface. For example, Watanabe et al. (The 2nd InζConf, onMod
ulated Sem1conductor 8tru
tures, Kyoto.

Japanti)、220(1985))の報告では、
有機金属気相成長法によるG a A s −A j 
G a A sのヘテロ界面の形状は、単原子層オーダ
の凹凸があり、その凹凸の大きさが成長温度820℃の
ときは30〜4QA、670℃のときは30QAである
。低温はど凹凸の形状が大きく、平坦性が良いことがわ
かる。しかしながら、結晶性を考慮すると低温成長にも
限界があり成長温度の最適化で得られる界面の平坦性に
限界があることがわかる。
Japanti), 220 (1985)),
G a A s - A j by organometallic vapor phase epitaxy
The shape of the heterointerface of GaAs has irregularities on the order of a monoatomic layer, and the magnitude of the irregularities is 30 to 4 QA when the growth temperature is 820°C, and 30QA when the growth temperature is 670°C. It can be seen that at low temperatures, the shape of the unevenness is large and the flatness is good. However, when crystallinity is considered, there is a limit to low-temperature growth, and it is clear that there is a limit to the flatness of the interface that can be obtained by optimizing the growth temperature.

(発明が解決しようとする間頂点) 以上の点を鑑み成長/マラメータの最適化によるヘテロ
界面の平坦性向上の限界を′うわまわる高度な平坦性を
実現せしむる有機金属気相成長法を提供することが本発
明の目的である。
(The pinnacle of what the invention is trying to solve) In view of the above points, we developed a metal organic vapor phase epitaxy method that achieves a high level of flatness that exceeds the limit of improving the flatness of the hetero interface by optimizing the growth/parameter. It is an object of the present invention to provide.

〔発明の構成〕[Structure of the invention]

(問題を解決するための手段) 本発明は、成長パラメータの中で界面の平坦性に最も影
響が大きいと考えられる成長互変を最適化するにカロえ
、ヘテロ界面においてエピタキシャル成長を中断するこ
とき弔い、界面の平坦性0向上金はかるものである。
(Means for Solving the Problem) The present invention aims to optimize the growth tautomerism, which is considered to have the greatest influence on the flatness of the interface among the growth parameters, and to avoid interrupting epitaxial growth at the heterointerface. However, it is important to improve the flatness of the interface.

(作用) ■−■族fヒ合吻半導体において成長温度を650℃以
下に下げると、成長表面の凹凸の島の大きさは先にも述
べたように300A以上になる。この時。
(Function) When the growth temperature is lowered to 650 DEG C. or less in a group (1)-(2) group F hybrid semiconductor, the size of the uneven islands on the growth surface becomes 300 A or more, as described above. At this time.

エピタキシャル成長を中断すれば、成長表面で凹凸の島
どうしが結合しさらに大きな島が形成される。しかし、
基板温度が650℃以下とかなり低温のため島どうしの
結合速度はおまり速くない。従って、成長中断を5分間
以上行ない、島どうしの結合を促進させる。
If epitaxial growth is interrupted, the uneven islands on the growth surface will join together to form even larger islands. but,
Since the substrate temperature is quite low, below 650° C., the bonding speed between the islands is not very fast. Therefore, growth is interrupted for 5 minutes or more to promote islet bonding.

このとき、成長中断時間が5分間以下である場合は、成
長中断の効果は顕著でなく、連@戊長の場合と大差ない
ヘテロ界面しか得ることができない、一方、高温、例え
ば800℃で結晶成長した場合の成長中断の効果は存在
するが、その結果得られるヘテロ界面の平坦性ば、むし
ろ成長中断を行なわず700℃で結晶成長した場合のヘ
テロ界面の平坦性に劣る。これは、基板温度が高いため
成長表面上での分子の運動速度が速く多はの運動エネル
ギーをもつでいるため、成長中断により成長表面上の凹
凸形状が安定し、潰合しさらに大きな島°になることが
さまたげられるためと考えられる。
At this time, if the growth interruption time is 5 minutes or less, the effect of growth interruption is not significant, and only a heterointerface can be obtained, which is not much different from that in the case of continuous @ Bocho. Although there is an effect of growth interruption when the crystal is grown, the flatness of the resulting heterointerface is rather inferior to the flatness of the heterointerface when the crystal is grown at 700° C. without growth interruption. This is because the molecules on the growth surface move at a high speed and have a large amount of kinetic energy due to the high substrate temperature, so when the growth is interrupted, the uneven shape on the growth surface becomes stable and collapses, resulting in even larger islands. This is thought to be because it hinders the ability to

従って、成長表面上の凹凸形状どおしの結合を促進しさ
らに大きな凹凸形状を形成するには、基板温度650℃
以下、成長中断時間5分以上が適しでいる。
Therefore, in order to promote the bonding between the uneven shapes on the growth surface and form even larger uneven shapes, the substrate temperature must be set at 650°C.
Below, a growth interruption time of 5 minutes or more is suitable.

上記のようにしで得られた平坦な成長表面上にヘテロ物
質?エピタキシャル氏長すれば、非常に良好な平坦性を
有するヘテロ界面を有機金属気相成長法で得ることがで
きる。
Heterogeneous material on the flat growth surface obtained as above? If the epitaxial length is increased, a heterointerface with very good flatness can be obtained by metal-organic vapor phase epitaxy.

(実施例) 以下1本発明の実施例を図面に去づいて具体的に説明す
る。
(Example) An example of the present invention will be specifically described below with reference to the drawings.

第1図は本発明を原料ガスとしてアルシン(Asへ)ト
リメチルガリウム(TMG)、)リメチルアルミニウム
(TMA)f、用いでGaAs−AJGaAsi子井戸
構造に応用した場合のガス70−シーケンスである。
FIG. 1 shows a gas 70-sequence when the present invention is applied to a GaAs-AJGaAsi child well structure using arsine (to As) trimethylgallium (TMG) and trimethylaluminum (TMA) f as source gases.

バリア1のAA’Asの混晶比セ0.34.ウェル唱の
厚さば25Aとした。ウェル層の成長の前後に5分間の
成長中断を行う。成長中断時には、成長表面から砒素の
再蒸発を保ぐため、アルシン(A s Hs)は流した
ままにする。基板1度は650℃とした。
The mixed crystal ratio of AA'As in barrier 1 is 0.34. The thickness of the well-singing bar was 25A. A growth interruption of 5 minutes is performed before and after the growth of the well layer. When growth is interrupted, arsine (A s Hs) is left flowing to maintain reevaporation of arsenic from the growth surface. The substrate temperature was 650°C.

11m比は200.成長速度はG a A sで1.8
 A /秒とした。
11m ratio is 200. The growth rate is 1.8 in Ga As.
A/sec.

次に上記の方法で成長した量子井戸と従来の方法(基板
@τ700℃、成長中断なし、池は同じ条件)で成長し
た量子井戸のヘテロ界面の平坦性をフォトルミネセンス
測定で評価した。フォトルミネセンス測定はAr+レー
ザを用い、液体ヘリウム温度で行った。
Next, the flatness of the heterointerface of the quantum well grown by the above method and the quantum well grown by the conventional method (substrate @ 700° C., no growth interruption, same pond conditions) was evaluated by photoluminescence measurement. Photoluminescence measurements were performed using an Ar+ laser at liquid helium temperature.

フォトルミネセンスの測定結果を第2図に示す。Figure 2 shows the photoluminescence measurement results.

同図(a) d従来の方法で成長じた量子井戸からの発
光スペクトル、同図tb)は本発明による方法で成長し
た量子井戸からの発光スペクトルtホす。凹凸の大きさ
け〜200Aでちることがわかる。(文献J、シシ、に
、にバジャイ181チャウドウリ;Appl 、Phy
s、Lett、44.P、805(1984)参照)一
方、同図(b)では、スペクトルは3本に分離しており
、それぞれの半値幅けl::8meVであった。また、
そのスペクトルの分離波長は:6nmでありそれぞれの
ビークti単原子層(2,83A )だけ厚さの違り量
子井戸の@光に対応している。第3図にこのご子井戸の
ヘテロ界面の模式図を示す。ヘテロ界面の凹凸形状はエ
キシトンサイズ(250A径)より大きく、エキシトン
は同図に示すよりに、このご子井戸を単原子層だけ厚さ
の違う3つの量子井戸としで感する。その結果第2図(
b)のようなフオドルミネセンスのピーク分離が得られ
たのである。このナシ合ヰ3図よりわかるように、ヘテ
ロ界面の凹凸は少なくとも数百オングストロームあジ子
坦性が非常によいことがわかる。
Figures (a) and (d) show the emission spectrum from a quantum well grown by the conventional method, and (t) and (t) show the emission spectrum from a quantum well grown by the method of the present invention, respectively. It can be seen that it breaks down when the size of the unevenness is ~200A. (Reference J, Shishi, Ni, Ni Bajaj 181 Chaudhuri; Appl, Phy
s, Lett, 44. P., 805 (1984)) On the other hand, in the same figure (b), the spectrum was separated into three, each having a half-width of 1::8 meV. Also,
The separation wavelength of the spectrum is: 6 nm, and the thickness difference between each peak Ti monoatomic layer (2,83 A) corresponds to the @light of the quantum well. Figure 3 shows a schematic diagram of the heterointerface of this goko well. The uneven shape of the hetero interface is larger than the exciton size (250A diameter), and the exciton perceives this quantum well as three quantum wells that differ in thickness by a single atomic layer, rather than as shown in the figure. The results are shown in Figure 2 (
A peak separation of photoluminescence as shown in b) was obtained. As can be seen from FIG. 3, the unevenness of the hetero interface has very good zigzag flatness of at least several hundred angstroms.

〔発明の効果〕〔Effect of the invention〕

上記の結果より、本発明の手法を用いれば、非常Iで急
峻性の良く、かつ平坦性の良い■−■族化合物手・累本
のヘテロ界面を得ることができる。
From the above results, if the method of the present invention is used, it is possible to obtain a hetero-interface of a ■-■ group compound hand-joint that is very I, has good steepness, and has good flatness.

また、本宅明は叔畏中析という手法を用いるための成長
ガスの切れヲ良くすることができ、ヘテロ界面の1e、
液汁の向上にも幼果がある。
In addition, Akira Motoyaku was able to improve the cutting of the growth gas for using the method of sintering, and the heterointerface 1e,
There are also young fruits that improve the sap.

なお、4:色間:ま■−■族化合吻半導体つ有侵金属気
用成受去のみでなく、気相成長t(よるエピタキシャル
成長パ(もむ用できる。
Note that 4: Shiroma: M - - ■ Group compound semiconductors can be used not only for vapor deposition and removal of invasive metals, but also for epitaxial growth using vapor phase growth.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は有J及金4気相a長法に、しけるガスフローシ
ーケンスを示す図、遍2図はフォトルミネセンススペク
トルを示す図、第3図は量子井戸ヘテロ界面つ嘆式図で
ある。 5l−b 暉シ簡 (亡2 第  1  図 第  2 図
Figure 1 is a diagram showing the gas flow sequence according to the four-gas phase a-length method, Figure 2 is a diagram showing the photoluminescence spectrum, and Figure 3 is a diagram of the quantum well heterointerface. . 5l-b.

Claims (1)

【特許請求の範囲】[Claims] 所定の温度に保持した単結晶基板上に有機金属気相成長
法により、ヘテロ界面を含むIII−V族化合物半導体結
晶をエピタキシャル成長させる際に、該単結晶基板の温
度を650℃以下に保ち、該ヘテロ界面で5分間以上の
成長中断をすることを特徴とするエピタキシャル成長方
法。
When epitaxially growing a III-V group compound semiconductor crystal containing a heterointerface on a single crystal substrate held at a predetermined temperature by organometallic vapor phase epitaxy, the temperature of the single crystal substrate is kept at 650°C or less, and the An epitaxial growth method characterized by suspending growth for 5 minutes or more at a hetero interface.
JP24750886A 1986-10-20 1986-10-20 Epitaxial growth method Pending JPS63102222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24750886A JPS63102222A (en) 1986-10-20 1986-10-20 Epitaxial growth method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24750886A JPS63102222A (en) 1986-10-20 1986-10-20 Epitaxial growth method

Publications (1)

Publication Number Publication Date
JPS63102222A true JPS63102222A (en) 1988-05-07

Family

ID=17164520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24750886A Pending JPS63102222A (en) 1986-10-20 1986-10-20 Epitaxial growth method

Country Status (1)

Country Link
JP (1) JPS63102222A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02203520A (en) * 1989-02-01 1990-08-13 Sumitomo Electric Ind Ltd Growth of compound semiconductor crystal
JP4676100B2 (en) * 2001-08-07 2011-04-27 古河電気工業株式会社 Epitaxial growth method of Al-containing compound semiconductor layer
WO2020162334A1 (en) 2019-02-04 2020-08-13 スミダコーポレーション株式会社 Coil component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02203520A (en) * 1989-02-01 1990-08-13 Sumitomo Electric Ind Ltd Growth of compound semiconductor crystal
JP4676100B2 (en) * 2001-08-07 2011-04-27 古河電気工業株式会社 Epitaxial growth method of Al-containing compound semiconductor layer
WO2020162334A1 (en) 2019-02-04 2020-08-13 スミダコーポレーション株式会社 Coil component

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