JPH0370124A - Manufacture of iii-v compound semiconductor device having method structure - Google Patents
Manufacture of iii-v compound semiconductor device having method structureInfo
- Publication number
- JPH0370124A JPH0370124A JP20478489A JP20478489A JPH0370124A JP H0370124 A JPH0370124 A JP H0370124A JP 20478489 A JP20478489 A JP 20478489A JP 20478489 A JP20478489 A JP 20478489A JP H0370124 A JPH0370124 A JP H0370124A
- Authority
- JP
- Japan
- Prior art keywords
- group
- semiconductor
- semiconductor layer
- supply
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 19
- 150000001875 compounds Chemical class 0.000 title claims description 15
- 239000002994 raw material Substances 0.000 claims abstract description 26
- 229910021478 group 5 element Inorganic materials 0.000 claims abstract description 20
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 3
- 125000002524 organometallic group Chemical group 0.000 claims description 2
- 125000005842 heteroatom Chemical group 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 125000004429 atom Chemical group 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000007789 gas Substances 0.000 description 11
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 7
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 7
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 7
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical group [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- JOTBHEPHROWQDJ-UHFFFAOYSA-N methylgallium Chemical compound [Ga]C JOTBHEPHROWQDJ-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は、ヘテロ構造を有する■−Ｖ族化合物半導体装
置の製造方法に関し、
有機金属気相成長法による量子井戸作製方法を改良し、
より理想的に急峻なヘテロ界面を有する量子井戸構造を
作製できる■−■族化合物半導体装置の製造方法を提供
することを目的とし、有機金属気相成長法を用いて、２
種類の■−■族化合物半導体の層を積層してヘテロ構造
を形成する工程を含む化合物半導体装置の製造方法にお
いて、一方の半導体の層上に他方の半導体の層を形成す
る際に、上記一方の半導体の■族元素原料ガスの供給を
停止した後に上記一方の半導体のＶ族元素原料ガスの供
給を停止することによって上記一方の半導体層の最表面
をその半導体のＶ族元素で形成し、次に上記他方の半導
体の■族元素原料ガスの供給を開始してから、この■族
元素の１原子層が上記最表面上に形成されるのに要する
よりも短い時間の経過後に、上記他方の半導体装置族元
素原料ガスの供給を開始するように構成する。[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing a ■-V group compound semiconductor device having a heterostructure, and includes the following steps:
The purpose of this is to provide a method for manufacturing a ■-■ group compound semiconductor device that can create a quantum well structure with a more ideally steep heterointerface.
In a method for manufacturing a compound semiconductor device including a step of stacking layers of group ■-■ compound semiconductors to form a heterostructure, when forming a layer of one semiconductor on a layer of the other semiconductor, one of the above forming the outermost surface of the one semiconductor layer with the group V element of the semiconductor by stopping the supply of the group V element raw material gas of the one semiconductor after stopping the supply of the group V element raw material gas of the semiconductor; Next, after starting the supply of the group Ⅰ element raw material gas for the other semiconductor, and after a period of time shorter than that required for one atomic layer of the group Ⅰ element to be formed on the outermost surface, The system is configured to start supplying the semiconductor device group element raw material gas.
本発明は、ヘテロ構造を有するＩ−Ｖ族化合物半導体装
置の製造方法に関する。The present invention relates to a method for manufacturing a group IV compound semiconductor device having a heterostructure.
ヘテロ構造を有する■−■族化合物半導体装置の代表的
なものは、ＩｎＰ基板上に第１の半導体層１ｎＧａＡｓ
あるいはＩｎＧａＡｓｐを量子井戸層として形成し、第
１の半導体層よりも大きなエネルギーギャップを有する
第２の半導体層ＩｎＰあるいはＩｎＧａＡｓＰを障壁層
として形成した量子井戸構造を有する。このような構造
は有機金属気相成長（ＭＯＶＰＢ）法を用いて形成され
ており、量子井戸を用いる素子の性能を向上させるため
に、より急峻なヘテロ界面を有する構造を作製すること
が要求されている。A typical type of a ■-■ group compound semiconductor device having a heterostructure is a first semiconductor layer of 1nGaAs on an InP substrate.
Alternatively, it has a quantum well structure in which InGaAsp is formed as a quantum well layer and a second semiconductor layer InP or InGaAsP having a larger energy gap than the first semiconductor layer is formed as a barrier layer. Such structures are formed using metal organic vapor phase epitaxy (MOVPB), and in order to improve the performance of devices using quantum wells, it is required to create structures with steeper heterointerfaces. ing.
従来、ＭＯＶＰＢ法を用いて量子井戸構造を作製する際
には第２図に示すようなタイムテーブルに従って結晶成
長を行なってきた。Conventionally, when producing a quantum well structure using the MOVPB method, crystal growth has been performed according to a timetable as shown in FIG.
すなわち、第１の半導体層の■族元素原料の供給を停止
し、この層の成長を中断し、■族元素原料の反応室から
のパージを終了しかつこの層の最表面をこの半導体の■
族元素で形成した後に、■族元素原料ガスの供給を停止
し、次に第２の半導体層のＶ族元素原料の供給を開始し
、反応室から第１の半導体層の■族元素原料をパージし
終ったのち、■族元素原料の供給を開始し、第２の半導
体層の成長を行なう。また第２の半導体層から第１の半
導体層へのへテロ界面作製時にも同様の操作を行なう。That is, the supply of the group (III) element raw material for the first semiconductor layer is stopped, the growth of this layer is interrupted, the purge of the group (III) element raw material from the reaction chamber is completed, and the outermost surface of this layer is
After the formation with the group element, the supply of the group Ⅰ element raw material gas is stopped, then the supply of the group V element raw material for the second semiconductor layer is started, and the group Ⅰ element raw material for the first semiconductor layer is supplied from the reaction chamber. After purging is completed, the supply of the group (Ⅰ) element raw material is started, and the second semiconductor layer is grown. A similar operation is also performed when forming a heterointerface from the second semiconductor layer to the first semiconductor layer.
ところがこの従来の成長法の場合、第１の半導体層と第
２の半導体層のそれぞれのＶ族元素組成が異なるとき、
第１の半導体層の表面を第２の■族供給元素がたたき、
第１の半導体層の表面の■族原子の１部が第２のＶ族供
給元素と置換してしまう。また、第２の半導体層の表面
を第１のＶ族供給元素がたたき、第２の半導体層の表面
のＶ族原子の１部が第１のＶ族供給元素と置換してしま
う。その結果、理想的に急峻な組成プロファイルをもつ
ヘテロ界面は作製できず、理論的に予想される量子効果
を十分に素子特性に生かすことができなかった。このＶ
族元素の置換過程の模式図を第３図に示した。同図はＩ
ｎＰ上に成長するＩｎＧａＡｓ／ＩｎＰヘテロ界面の場
合を示している。However, in the case of this conventional growth method, when the first semiconductor layer and the second semiconductor layer have different group V element compositions,
The surface of the first semiconductor layer is hit by a second group-supplying element,
A part of the group (II) atoms on the surface of the first semiconductor layer are replaced with the second group V supply element. Furthermore, the first group V supply element hits the surface of the second semiconductor layer, and a portion of the group V atoms on the surface of the second semiconductor layer are replaced with the first group V supply element. As a result, it was not possible to create a heterointerface with an ideally steep composition profile, and it was not possible to fully utilize theoretically predicted quantum effects in device characteristics. This V
A schematic diagram of the group element substitution process is shown in FIG. The figure is I
The case of an InGaAs/InP heterointerface grown on nP is shown.
このように、ヘテロ界面の組成プロフィルが理想的に急
峻でないため、レーザ素子や光変調器等の量子井戸構造
を用いた素子において、量子効果に起因する素子特性を
十分に実現することができないという問題があった。In this way, it is said that because the composition profile of the hetero interface is not ideally steep, devices using quantum well structures such as laser devices and optical modulators cannot fully realize the device characteristics caused by quantum effects. There was a problem.
本発明は、ＭＯＶＰＩＥ法による量子井戸作製方法を改
良し、より理想的に急峻なヘテロ界面を有する量子井戸
構造を作製できる■−■族化合物半導体装置の製造方法
を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to improve the quantum well fabrication method using the MOVPIE method and provide a method for fabricating a ■-■ group compound semiconductor device that can fabricate a quantum well structure having a more ideally steep heterointerface.
上記の目的は、本発明によれば、有機金属気相成長法を
用いて、２種類の■−■族化合物半導体の層を積層して
ヘテロ構造を形成する工程を含む化合物半導体装置の製
造方法において、一方の半導体の層上に他方の半導体の
層を形成する際に、上記一方の半導体の■族元素原料ガ
スの供給を停止した後に上記一方の半導体のＶ族元素原
料ガスの供給を停止することによって上記一方の半導体
層の最表面をその半導体のＶ族元素で形成し、次に上記
他方の半導体の■族元素原料ガスの供給を開始してから
、この■族元素のｌ原子層が上記最表面上に形成される
のに要するよりも短い時間の経過後に、上記他方の半導
体のＶ族元素原料ガスの供給を開始することを特徴とす
るヘテロ構造を有する■−Ｖ族化合物半導体装置の製造
方法によって達成される。The above object, according to the present invention, is a method for manufacturing a compound semiconductor device, which includes a step of stacking two types of ■-■ group compound semiconductor layers to form a heterostructure using an organometallic vapor phase epitaxy method. When forming a layer of one semiconductor on a layer of the other semiconductor, after stopping the supply of the Group I element raw material gas of the one semiconductor, stopping the supply of the Group V element raw material gas of the one semiconductor. By doing so, the outermost surface of the one semiconductor layer is formed with a Group V element of that semiconductor, and then after starting the supply of the Group Ⅰ element raw material gas of the other semiconductor, the L atomic layer of the Group Ⅰ element is formed. ■-V group compound semiconductor having a heterostructure, characterized in that supply of the group V element raw material gas for the other semiconductor is started after a time shorter than that required for formation on the outermost surface. This is achieved by a method of manufacturing the device.
本発明のＭＯＶＰＢ法は、２種の異なるＶ族元素組成を
有する半導体層からなる量子井戸構造の作製において、
第１図に示したタイムテーブルに従った原料供給を行な
う。In the MOVPB method of the present invention, in the production of a quantum well structure consisting of semiconductor layers having two different group V element compositions,
Raw materials are supplied according to the timetable shown in FIG.
まず第１の半導体層の■族元素原料の供給を止め、第１
の半導体層の成長中断を行なう。時間ｔｌの間■族元素
原料の反応室からのパージを行ない、■族元素原料の供
給を停止する。次に第２の半導体層の■族元素原料の供
給を開始する。■族元素原料の供給前に数秒の全ての原
料供給が停止する時間があってもよい。第１の半導体層
の表面に第２の半導体層の■族元素が１原子層成長する
時間より短かい時間ｔ２のあと、第２の半導体層の■族
元素原料の供給を開始し、第２の半導体層の成長を行な
う。第２の半導体層から第１の半導体層へと移るときに
も、同様の操作を行なう。First, the supply of group Ⅰ element raw material for the first semiconductor layer is stopped, and
The growth of the semiconductor layer is interrupted. During the time tl, the group (2) element raw material is purged from the reaction chamber, and the supply of the group (2) element raw material is stopped. Next, supply of the group (Ⅰ) element raw material for the second semiconductor layer is started. There may be a period of several seconds during which the supply of all raw materials is stopped before supplying the Group (2) element raw materials. After a time t2, which is shorter than the time required for one atomic layer of the group III element of the second semiconductor layer to grow on the surface of the first semiconductor layer, supply of the group III element raw material for the second semiconductor layer is started, and A semiconductor layer is grown. A similar operation is performed when moving from the second semiconductor layer to the first semiconductor layer.
本発明の成長法を用いれば、第１の半導体層の最表面の
■鉄原子は第２の半導体層のＶ族元素と置換されること
が全くない。また第２の半導体層の最表面のＶ鉄原子は
第１の半導体層のＶ族元素と置換されることが全くない
。If the growth method of the present invention is used, the iron atoms on the outermost surface of the first semiconductor layer will never be replaced with group V elements in the second semiconductor layer. Further, the V iron atoms on the outermost surface of the second semiconductor layer are never replaced with group V elements of the first semiconductor layer.
また第１の半導体層上に供給する第２の半導体層の■族
元素と第２の半導体層上に供給する第１の半導体層の■
族元素の、それのみを供給する時間をそれぞれ、１原子
成長時間より短かく区切ったため、■族元素の金属ドロ
ブレットが生じることがない。Furthermore, the group Ⅰ element of the second semiconductor layer supplied on the first semiconductor layer and the group ① element of the first semiconductor layer supplied on the second semiconductor layer are
Since the time for supplying only the group elements is divided into periods shorter than the one-atom growth time, metal droplets of the group (Ⅰ) elements do not occur.
その結果、非常に急峻なヘテロ界面を有する量子井戸構
造の作製が可能となる。As a result, it becomes possible to fabricate a quantum well structure with a very steep heterointerface.
本発明にしたがってＩｎＧａＡｓ／ＩｎＰ多重量子井戸
構造を作製する例を説明する。An example of fabricating an InGaAs/InP multiple quantum well structure according to the present invention will be described.
Ｖ族元素組成が１００％Ｐから１００％Ａｓに切り換わ
るこの材料の組み合わせは、急峻なヘテロ界面の作製が
最も困難なＩｎＰ系量子井戸構造の典型例であり、Ｖ族
元素原料の気相中の分圧や成長温度の最適化を要する。This combination of materials in which the group V element composition switches from 100% P to 100% As is a typical example of an InP-based quantum well structure in which it is most difficult to create a steep hetero interface, and it It is necessary to optimize the partial pressure and growth temperature.
この材料の組み合せの場合、ＩｎＰ成長における供給原
料としてはトリメチルインヂウム（ＴＭＩｎ） 、フォ
スフイン（ＰＨ３＞を用いる。成長速度は０．６ ｊａ
／ｈｏｕｒ程度、ＰＨ３）気相中の供給分圧はＱ、 ３
ｔｏｒｒ程度がよい。またＩｎＧａＡｓ成長における
供給原料としては、ＴＭＩｎ、 ） ！Ｊメチルガリ
ウム（ＴＥＧａ） 、アルシン（ＡｓＨ３）を用いる。In the case of this combination of materials, trimethylindium (TMIn) and phosphine (PH3>) are used as feed materials for InP growth.The growth rate is 0.6 ja
/hour, PH3) The supply partial pressure in the gas phase is Q, 3
Torr level is good. In addition, the feedstock for InGaAs growth is TMIn, )! J methyl gallium (TEGa) and arsine (AsH3) are used.
成長速度は０．６μ／ ｈ ｏ ｕ ｒ程度、ＡｓＨ，
の気相中の供給分圧はＱ、 ｌ ｔｏｒｒ程度がよい。The growth rate is about 0.6μ/hour, AsH,
The supply partial pressure in the gas phase is preferably about Q, l torr.
成長圧力は０．１気圧程度、成長温度は５５０〜５８０
℃程度がよい。Growth pressure is about 0.1 atm, growth temperature is 550-580℃.
The temperature should be around ℃.
それぞれのＩｎＰ （Ｉ ｎＧａＡｓ ）半導体層にＩ
ｎＧａＡｓ （Ｉ ｎＰ ）半導体層を形成する際に、
まずＴＭＩｎ（ＴＭＩｎ ＋ＴＥＧａ）の供給を止め、
ＩｎＰ （Ｉ ｎＧａＡｓ ）の成長を中断する。I in each InP (InGaAs) semiconductor layer
When forming the nGaAs (I nP) semiconductor layer,
First, stop the supply of TMIn (TMIn +TEGa),
The growth of InP (InGaAs) is interrupted.
３〜５ＳｅＣのＰＨ３（ＡｓＨ３）雰囲気での成長中断
後、ＰＨ３（ＡｓＨ３）の供給を停止し、ＴＭＩｎ ＋
Ｔ８Ｇａ （ＴＭＩｎ）の供給を開始する。この間にＨ
２あるいは他の不活性ガスによる数秒以下のパージをは
さんでもよい。After suspending growth in a PH3 (AsH3) atmosphere of 3 to 5 SeC, the supply of PH3 (AsH3) was stopped and TMIn +
Start supplying T8Ga (TMIn). During this time H
2 or other inert gas for several seconds or less.
■族元素原料の供給開始後０．３〜０．７ ｓｅｃでＡ
ｓＨ。■A in 0.3 to 0.7 sec after the start of supply of group element raw materials
sH.
（ＰＨ３）の供給を開始し、ＩｎＧａＡｓ （Ｉ ｎＰ
）層の成長を開始する。(PH3) was started, and InGaAs (I nP
) starts layer growth.
上記成長性によって極めて理想的に急峻なヘテロ界面を
有するＩｎＧａＡｓ／ＩｎＰ量子井戸構造が作製できる
。The growth properties described above make it possible to fabricate an InGaAs/InP quantum well structure having an extremely ideal steep hetero interface.
以上説明したように、本発明によって極めて急峻なヘテ
ロ界面を有する量子井戸構造を作製できるようになり、
量子井戸構造を利用するＩ−Ｖ族化合物半導体素子の特
性向上に寄与するところが大きい。As explained above, the present invention makes it possible to fabricate a quantum well structure with an extremely steep hetero interface.
This greatly contributes to improving the characteristics of IV group compound semiconductor devices that utilize quantum well structures.
第１図は、本発明にしたがってヘテロ構造を形成する過
程を示すグラフ、
第２図は、従来のへテロ構造形成過程を示すグラフ、お
よび
第３図は、Ｖ鉄原子の置換を示す模式図である。FIG. 1 is a graph showing the process of forming a heterostructure according to the present invention, FIG. 2 is a graph showing the conventional process of forming a heterostructure, and FIG. 3 is a schematic diagram showing the substitution of V iron atoms. It is.
Claims (1)
化合物半導体の層を積層してヘテロ構造を形成する工程
を含む化合物半導体装置の製造方法において、一方の半
導体の層上に他方の半導体の層を形成する際に、上記一
方の半導体のIII族元素原料ガスの供給を停止した後に
上記一方の半導体のＶ族元素原料ガスの供給を停止する
ことによって上記一方の半導体層の最表面をその半導体
のＶ族元素で形成し、次に上記他方の半導体のIII族元
素原料ガスの供給を開始してから、このIII族元素の１
原子層が上記最表面上に形成されるのに要するよりも短
い時間の経過後に、上記他方の半導体のＶ族元素原料ガ
スの供給を開始することを特徴とするヘテロ構造を有す
るIII−Ｖ族化合物半導体装置の製造方法。1. In a method for manufacturing a compound semiconductor device that includes a step of stacking layers of two types of III-V compound semiconductors to form a heterostructure using organometallic vapor phase epitaxy, When forming the layer of the other semiconductor, the supply of the group III element source gas for the one semiconductor is stopped, and then the supply of the group V element source gas for the one semiconductor is stopped, thereby forming the layer of the one semiconductor layer. After forming the outermost surface with a group V element of the semiconductor, and then starting supply of the group III element raw material gas of the other semiconductor, one of the group III elements is formed.
III-V group having a heterostructure, characterized in that supply of the group V element raw material gas for the other semiconductor is started after a period of time shorter than that required for an atomic layer to be formed on the outermost surface. A method for manufacturing a compound semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20478489A JPH0370124A (en) | 1989-08-09 | 1989-08-09 | Manufacture of iii-v compound semiconductor device having method structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20478489A JPH0370124A (en) | 1989-08-09 | 1989-08-09 | Manufacture of iii-v compound semiconductor device having method structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0370124A true JPH0370124A (en) | 1991-03-26 |
Family
ID=16496291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20478489A Pending JPH0370124A (en) | 1989-08-09 | 1989-08-09 | Manufacture of iii-v compound semiconductor device having method structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0370124A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6833161B2 (en) * | 2002-02-26 | 2004-12-21 | Applied Materials, Inc. | Cyclical deposition of tungsten nitride for metal oxide gate electrode |
| US7732325B2 (en) | 2002-01-26 | 2010-06-08 | Applied Materials, Inc. | Plasma-enhanced cyclic layer deposition process for barrier layers |
| US7781326B2 (en) | 2001-02-02 | 2010-08-24 | Applied Materials, Inc. | Formation of a tantalum-nitride layer |
| US10280509B2 (en) | 2001-07-16 | 2019-05-07 | Applied Materials, Inc. | Lid assembly for a processing system to facilitate sequential deposition techniques |
-
1989
- 1989-08-09 JP JP20478489A patent/JPH0370124A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7781326B2 (en) | 2001-02-02 | 2010-08-24 | Applied Materials, Inc. | Formation of a tantalum-nitride layer |
| US10280509B2 (en) | 2001-07-16 | 2019-05-07 | Applied Materials, Inc. | Lid assembly for a processing system to facilitate sequential deposition techniques |
| US7732325B2 (en) | 2002-01-26 | 2010-06-08 | Applied Materials, Inc. | Plasma-enhanced cyclic layer deposition process for barrier layers |
| US6833161B2 (en) * | 2002-02-26 | 2004-12-21 | Applied Materials, Inc. | Cyclical deposition of tungsten nitride for metal oxide gate electrode |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4963816B2 (en) | Nitride semiconductor device manufacturing method and light emitting device | |
| US6352884B1 (en) | Method for growing crystals having impurities and crystals prepared thereby | |
| JPH0370124A (en) | Manufacture of iii-v compound semiconductor device having method structure | |
| JP3137767B2 (en) | Method for manufacturing semiconductor device | |
| JPH11112102A (en) | Fabrication of optical semiconductor device | |
| JPH0431396A (en) | Growth of semiconductor crystal | |
| JP2743443B2 (en) | Compound semiconductor vapor growth method and apparatus | |
| JP3013992B2 (en) | Method for growing compound semiconductor crystal | |
| JPH07335988A (en) | Compd. semiconductor device and production process thereof | |
| JPH05335241A (en) | Compound semiconductor and manufacture thereof | |
| JP2991074B2 (en) | Metalorganic vapor phase epitaxy | |
| JP4002323B2 (en) | Method for producing compound semiconductor | |
| JPS63102222A (en) | Epitaxial growth method | |
| JP3109149B2 (en) | Compound semiconductor crystal growth method | |
| JP3098371B2 (en) | Semiconductor crystal growth method | |
| JP3464161B2 (en) | Method of manufacturing InP-based distributed feedback semiconductor laser | |
| JPH1074704A (en) | Manufacture of epitaxial wafer | |
| JP2722489B2 (en) | Semiconductor crystal growth method | |
| JPH0817739A (en) | Crystal growth method | |
| US20070281383A1 (en) | Method of manufacturing semiconductor multilayer structure | |
| JPH0334536A (en) | Manufacture of iii-v compound semiconductor element | |
| JPH02156522A (en) | Manufacture of semiconductor device | |
| JPH06140345A (en) | Manufacture of compound semiconductor device | |
| JPH07297134A (en) | Selective growth method for compound semiconductor | |
| KR20030016034A (en) | Two-step growth interruption process for control of semiconductor quantum dot |