JPS63100771A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS63100771A JPS63100771A JP61246651A JP24665186A JPS63100771A JP S63100771 A JPS63100771 A JP S63100771A JP 61246651 A JP61246651 A JP 61246651A JP 24665186 A JP24665186 A JP 24665186A JP S63100771 A JPS63100771 A JP S63100771A
- Authority
- JP
- Japan
- Prior art keywords
- transfer
- transistor
- driver
- size
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims 2
- 230000003068 static effect Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 2
- 230000003190 augmentative effect Effects 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 241000792276 Drino Species 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
Landscapes
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 不発明はスタテックメモリのセル構造に関する。[Detailed description of the invention] [Industrial application field] The invention relates to the cell structure of static memory.
スタテックメモリセルでは、正常な書き込み。 Normal writing in static memory cells.
読み出し動作を行なわせるためには、ドライノ(−トラ
ンジスタとトランスフチトランジスタの電流能力比を3
:1程度にしなければならず、そのため従来は、第2図
に示すごとく、ドライノ(−〇トランジスタのゲート巾
を、トランスファートランジスタより大きくして対応し
ていた。In order to perform a read operation, the current capacity ratio of the dryno transistor and the trans-edge transistor must be set to 3.
:1, and for this reason, conventionally, the gate width of the Drino (-) transistor was made larger than that of the transfer transistor, as shown in FIG.
上述した従来のスタテックメモリセルでは、ドライバー
トランジスタのゲート巾を大きくするため、メモリセル
面積が大きくなり、大′#量化を進める上で、大きな障
害になってきている。In the conventional static memory cell described above, since the gate width of the driver transistor is increased, the memory cell area increases, which has become a major obstacle in increasing the number of memory cells.
本発明は、ドライバートランジスタとトランスファトラ
ンジスタのモビリティ、ゲート膜厚1表面濃度などを異
ならせることにより、ドライバートランジスタのゲート
巾をトランス7テトランジスタのゲート巾迄小さくして
も、正常な書き込み、読み出し動作を行なわせることを
可能することを目的にしている。The present invention enables normal write and read operations even if the gate width of the driver transistor is reduced to the gate width of the transformer transistor by making the mobility, gate film thickness, surface concentration, etc. of the driver transistor and transfer transistor different. The purpose is to make it possible to do the following.
本発明に依れば、各トランジスタのサイズを、微細化技
術で決まるレイアワト設計基準の最小サイズまで小きく
することができ、セルサイズ、チップサイズの縮小比に
大きな効果を発揮する。According to the present invention, the size of each transistor can be reduced to the minimum size of the layout design standard determined by miniaturization technology, and a large effect is exerted on the reduction ratio of cell size and chip size.
第1図に本発明を実施したスタテックメモリセルのレイ
アワト例を示す。従来例と比べれば85チのセル面積に
なっている。本発明を渠現する第1の方法ri、)ラン
スフッ−トランジスタのゲート部にゲート?4極形成後
X線や、紫外線を照射し、界面準位を増やしモビリティ
を元来の1/3にする。第2の方法はトランス7丁−ト
ランジスタのゲート酸化膜厚をドライバートランジスタ
の3倍にする。このとき、それぞれのトランジスタのし
きい値をイオン注入でalt1!!I L、最適動作可
能な値に設定する。第3のフj法は、トランスファート
ランジスタの表面不純動線Kを増やし、トランジスタの
オン電流に1/3にする。わるいL上記3方法を組合わ
せて用いてもかまわない。FIG. 1 shows an example layout of a static memory cell embodying the present invention. Compared to the conventional example, the cell area is 85 inches. A first method of implementing the present invention: ri) A gate in the gate part of a transistor? After forming the quadrupole, it is irradiated with X-rays or ultraviolet rays to increase the interface level and reduce the mobility to one-third of its original level. The second method is to make the gate oxide film thickness of the seven transformer transistors three times that of the driver transistor. At this time, the threshold value of each transistor is changed by ion implantation to alt1! ! IL, set to a value that allows optimal operation. In the third method, the surface impurity flow line K of the transfer transistor is increased to reduce the on-state current of the transistor to 1/3. Bad L The above three methods may be used in combination.
なお本実九例では、ドライバートランジスタと、トラン
ス7丁−トランジスタのサイズを全く同一にしているが
、必ずしもこうする必*はなく、セルサイズ縮小の目的
を達成できるならば、若干トランジスタのサイズが変っ
ていてももちろんかまわない。In this example, the size of the driver transistor and the seven transformers are exactly the same, but it is not necessary to do so, and if the purpose of reducing the cell size can be achieved, the size of the transistor can be slightly increased. Of course, it doesn't matter if it changes.
第1図は本発明を適用したスタテックメモリセルのアル
ミ電極形成前の平面図、第2図は従来のスタテックメモ
リセルのアルミ電極形成前の平面図である。
1・・・・・・拡散層、2・・・・・・ポリシリコンゲ
ート電極、3・・・・・・コンタクト開孔。FIG. 1 is a plan view of a static memory cell to which the present invention is applied before aluminum electrodes are formed, and FIG. 2 is a plan view of a conventional static memory cell before aluminum electrodes are formed. 1... Diffusion layer, 2... Polysilicon gate electrode, 3... Contact opening.
Claims (1)
ジスタおよびドライバートランジスタ共にほぼ同一のゲ
ート巾を有していることを特徴とする半導体メモリ装置
。A semiconductor memory device characterized in that in a static memory cell, both a transfer transistor and a driver transistor have substantially the same gate width.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61246651A JPS63100771A (en) | 1986-10-17 | 1986-10-17 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61246651A JPS63100771A (en) | 1986-10-17 | 1986-10-17 | Semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63100771A true JPS63100771A (en) | 1988-05-02 |
Family
ID=17151587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61246651A Pending JPS63100771A (en) | 1986-10-17 | 1986-10-17 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63100771A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0531261U (en) * | 1991-10-01 | 1993-04-23 | ソニー株式会社 | Semiconductor memory |
US5880753A (en) * | 1990-02-19 | 1999-03-09 | Canon Kabushiki Kaisha | Temperature compensation apparatus and recording head and apparatus using the same |
US6812534B2 (en) | 2002-09-10 | 2004-11-02 | Renesas Technology Corp. | Static semiconductor memory device |
-
1986
- 1986-10-17 JP JP61246651A patent/JPS63100771A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5880753A (en) * | 1990-02-19 | 1999-03-09 | Canon Kabushiki Kaisha | Temperature compensation apparatus and recording head and apparatus using the same |
JPH0531261U (en) * | 1991-10-01 | 1993-04-23 | ソニー株式会社 | Semiconductor memory |
US6812534B2 (en) | 2002-09-10 | 2004-11-02 | Renesas Technology Corp. | Static semiconductor memory device |
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