JPS63100771A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To scale down cell size and chip size by forming a transfer transistor (TR) in a static memory cell and a driver TR in the same gate width. CONSTITUTION:A gate electrode 2 is shaped to a gate section for a transfer TR in a static memory cell, X-rays and ultraviolet rays are projected and an interface level is increased, and mobility is reduced to one third. Or the thickness of a gate oxide film in the transfer TR is trebled to a driver TR. The surface impurity concentration of the transfer TR is augmented, and ON currents of the TR is reduced to one third. Or these methods are combined, and the size of the driver TR and the transfer TR is equalized.

Description

[Detailed description of the invention] [Industrial application field] The invention relates to the cell structure of static memory.

[Conventional technology]

Normal writing in static memory cells.

In order to perform a read operation, the current capacity ratio of the dryno transistor and the trans-edge transistor must be set to 3.
:1, and for this reason, conventionally, the gate width of the Drino (-) transistor was made larger than that of the transfer transistor, as shown in FIG.

[Problems where inventions abound]

In the conventional static memory cell described above, since the gate width of the driver transistor is increased, the memory cell area increases, which has become a major obstacle in increasing the number of memory cells.

[Means for resolving issues]

The present invention enables normal write and read operations even if the gate width of the driver transistor is reduced to the gate width of the transformer transistor by making the mobility, gate film thickness, surface concentration, etc. of the driver transistor and transfer transistor different. The purpose is to make it possible to do the following.

According to the present invention, the size of each transistor can be reduced to the minimum size of the layout design standard determined by miniaturization technology, and a large effect is exerted on the reduction ratio of cell size and chip size.

〔Example〕

FIG. 1 shows an example layout of a static memory cell embodying the present invention. Compared to the conventional example, the cell area is 85 inches. A first method of implementing the present invention: ri) A gate in the gate part of a transistor? After forming the quadrupole, it is irradiated with X-rays or ultraviolet rays to increase the interface level and reduce the mobility to one-third of its original level. The second method is to make the gate oxide film thickness of the seven transformer transistors three times that of the driver transistor. At this time, the threshold value of each transistor is changed by ion implantation to alt1! ! IL, set to a value that allows optimal operation. In the third method, the surface impurity flow line K of the transfer transistor is increased to reduce the on-state current of the transistor to 1/3. Bad L The above three methods may be used in combination.

In this example, the size of the driver transistor and the seven transformers are exactly the same, but it is not necessary to do so, and if the purpose of reducing the cell size can be achieved, the size of the transistor can be slightly increased. Of course, it doesn't matter if it changes.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a static memory cell to which the present invention is applied before aluminum electrodes are formed, and FIG. 2 is a plan view of a conventional static memory cell before aluminum electrodes are formed. 1... Diffusion layer, 2... Polysilicon gate electrode, 3... Contact opening.

Claims (1)

[Claims] A semiconductor memory device characterized in that in a static memory cell, both a transfer transistor and a driver transistor have substantially the same gate width.