JPS6299980A - Signal transmission equipment - Google Patents

Abstract

PURPOSE:To simplify the circuit configuration of a signal transmission, equipment by providing a level fixing switching element which fixes the level of a signal line and adopting a two-input type inverter circuit which inputs signals and control signals on the signal line. CONSTITUTION:In the readout circuit RAi of an SRAM device, an output fixing MOSFET Q13 is provided between a supply voltage terminal VCC and signal line 8. When a selection controlling signal phiri is low in level, a cut-off MOSFET Q11 is turned off and the MOSFET Q13 is turned on. Moreover, the level of the signal line 8 inputted to the gate of an inverter circuit 12 is fixed at a high level. As a result, MOSFETs Q9 and Q10 are turned off and the readout circuit RAi is set to a nonselected state. When the signal phiri is high in level, the signal line 8 is released from the state where the signal line 8 is fixed to the high level and can follow the output level state of a sense amplifier SA. As a result, the readout circuit RAi is set to a selected state. Therefore, necessity of a cut-off MOSFET to be connected in series with the (p) channel MOSFET Q9 can be eliminated.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a signal transmission device that selectively transmits a signal based on a control signal, for example, a signal transmission device that transmits a signal selectively based on a control signal. The present invention relates to a technology that is effective when used in a readout circuit that selectively outputs the output from the device to an output terminal.

[Background technology]

As the bit capacity of memories such as SRAM increases, the number of memory mats tends to increase. In order to speed up the operation of such a memory, a configuration is being considered in which, for example, a sense amplifier is provided corresponding to each memory mat, and the output from the sense amplifier is selectively outputted to an output terminal.

Such alternative signal transmission is possible, for example, by the use of a circuit such as a clocked inverter circuit that is selectively activated between the output of each sense amplifier and a common signal line. becomes.

Here, the clocked inverter circuit includes one, for example, two MOSFETs that are operated complementary to each other by an input signal;
It is composed of two switches MO8FET or cut-off MO8FET connected in series with those MOSFETs and controlled in synchronization with each other.

In this case, the two MOSFETs that are operated in a complementary manner by the input signal have their respective apparent transconductances reduced in accordance with the non-negligible on-resistance of the cut-off MO8FETs connected in series to each MOSFET.

Therefore, the driving ability for the common signal line becomes small. Also, two cutoff MO3FETs are provided in the circuit.

Furthermore, since a circuit such as an inverter circuit is required to operate these two cutoff MO8FETs, the number of required MOSFETs increases and the circuit configuration of the device becomes complicated.

[Purpose of the invention]

An object of the present invention is to simplify the circuit configuration,
As a result, it is an object of the present invention to provide a signal transmission device that can achieve a non-selected state of signal transmission at high speed without delay.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, two MOs are operated in a complementary manner according to the input signal.
One of the SFETs is provided with a first cutoff MOSFET connected in series with it, and a second cutoff MOSFET is provided that makes the other input of the two MOSFETs at the cutoff level, and the two MOSFETs are connected in series.
By turning off the other FET and turning off the first cut-off MO5FET, the circuit is brought into a non-operating state or a non-selected state.

This simplifies one circuit configuration, and as a result, the non-selected state of signal transmission can be achieved at high speed without delay.

〔Example〕

FIG. 1 shows a signal transmission device according to the present invention in an SR shown in FIG.
FIG. 2 is a circuit diagram showing an embodiment applied to a readout circuit RAi in an AM device. This readout circuit RAi includes a P-channel type MO8FETQ9 and an N-channel type M○5FETQ10, which input the output from the sense amplifier SA to the gate via the signal line 8, and the MO8FETQ1.
0&,: N-channel cutoff MO8FETQ connected in series and inputting the selection control signal φri to its gate
The inverter circuit 12 includes an inverter circuit 11. Furthermore, in order to fix the level of the signal line 8 to a high level based on a low level signal of the selection control signal φri which is intended to deselect this readout circuit RAi,
A P-channel type output fixing MO5FET Q13 is provided between the power supply voltage terminal "f-vcc" and the signal line 8.

In the readout circuit RAi configured as described above, first, when the selection control signal φri is set to a low level so as to deselect this readout circuit RAi, the selection control signal φ'j is inputted. Cut-off MOSF
ETQII is turned off. At the same time, an output fixing MO8FETQ13 to which the selection control signal φri is input
is turned on, and as a result, the level of the signal line 8 input to the gate of the inverter circuit 12 is fixed at a high level. Therefore, MO8FETQ9 and MO8FE
Since both TQIIs are in the off state, this read circuit RAi is put in the non-selected state.

Further, when the selection control signal φri is set to a high level so as to put the readout circuit RAi into the selected state or the operating state, the cutoff MO8FETQII that inputs the selection control signal φri is turned on, and Output fixing MO5F inputting the selection control signal φri
ETQ13 is turned off. As a result, the signal line 8 input to the inverter circuit 12 is released from the high level fixed state and can follow the output level state from the sense amplifier SA. In response, the selected state of read circuit RAi is achieved.

Since the readout circuit RAi of this embodiment is configured as described above, it is possible to eliminate the need for a cutoff MOS FET such as the one connected in series to the P-channel type MO8FETQ9, and the configuration of the inverter circuit 12 itself can be reduced accordingly. Simplified. Moreover, since the MOS, FETQ13 and Qll can be driven by one signal φri,
The readout circuit is further simplified. Furthermore, the overall circuit configuration can be changed to WMs, that is, MO8FETQ.
Since the cutoff MO8FET connected in series to 9 can be omitted, the operation of the readout circuit RAi can be made faster.

In this embodiment, although not particularly limited, the sense amplifier SA prevents wasteful current from flowing into the read circuit RAi through the MOSFET Q13 when it is in an inactive state, and also ensures that the signal line 8 has a good level. In order to set it to a high level, its operating state is controlled by a selection control signal φri.

FIG. 2 shows a specific circuit example of the sense amplifier SA. The sense amplifier SA is composed of N-channel differential MOSFETQ16. Q17, P-channel type MO8FET Q14 that constitutes the current mirror load. Q
15, and an N-channel MOSFETQ as a current source whose operations are controlled by a selection control signal φri.
Consists of i8. Differential MO8FETQ16 and Q17 (7
1 gate is given a complementary signal from a common data line, D, which will be explained later with reference to FIG.

With this configuration, the sense amplifier SA receives the selection control signal φ
If ri is high level, it is activated and MOSFETQ
16. A signal corresponding to the operating state of Q17 is output to the signal line 8. ``If the selection control signal φri is at a low level, the MOSFET Q18 is turned off accordingly, so the sense amplifier SA is rendered inactive. In this non-operating state, the operating current of MOSFETQ15 becomes substantially O in response to MOSFET018 being turned off, so MO8FETQ14 is turned off. In response, sense amplifier SA enters a high output impedance state.

FIG. 4 is a circuit diagram showing an example of an SRAM device equipped with the above readout circuit, and this SRAM device includes four memory arrays Mi (Ml, M2.M3°M4), and each memory array Mi Although details are not shown, it includes a plurality of static memory cells arranged in a matrix. Among the memory cells, those arranged in the same row have their selection terminals connected to the word lines corresponding to the respective rows, and those arranged in the same column have their data output terminals connected to the data lines corresponding to the respective columns. It is connected to the.

The word line is connected to an X decoder X, AD which forms a word line selection signal according to an X address signal. Furthermore, a Y decoder YAD is provided for the data line to form a data line selection signal in accordance with the Y address signal. Nine column switches C-S Wi (C-S W 1) are provided corresponding to each memory mat.
, C-S W 2 , C-S W3, C-5W4
) can address a predetermined memory cell by receiving a selection signal from the Y decoder YAD.

The column switch C-S Wi has a write circuit Wi (Wl, W2.W3.W4) and a read circuit RAi (RAI, RA2.RA3゜RA4) corresponding to each column switch.
is connected. The write circuit Wi is a control circuit C0NT supplied with two bits of the chip enable signal GE, the write enable signal WE, and the Y address signal.
The readout circuit Ri is connected to the control circuit C0NT, and its operation is controlled based on the control signal φvi (φs1.φ”2?φ, also φw4) formed by the control circuit C0NT.
Its operation is controlled based on the selection control signal φri (φrxtφr29 φr□, φr4) formed by the control circuit C0NT.

Of the Y address signal AYj, the 2-bit address signal supplied to the control circuit C0NT is regarded as a memory array selection signal. The outputs of the control signals φ%+i and φri are controlled by the memory array selection signal.

If the chip enable signal GE and the write enable signal WE are each set to low level, and the memory array selection signal instructs the memory array M1, the control signal φvi in other words instructs the memory to perform a data write operation. If the selection of memory array M1 is instructed, it is set to high level accordingly. The write circuit W1 is activated by setting the control signal φw1 to a high level, and outputs a complementary at signal corresponding to the data signal supplied via the data input terminal Din, the data input buffer DIB, and the common signal line C3LI. , common D-9 line and output to D. Common data line and 1
] The complementary data signal applied to the column switch C-
5WI to the memory array.

If the memory array selection signal instructs the selection of the memory array of the memory array selection signal, the control signal φS is
left at low level. The write circuit W1 is rendered inactive by the control signal φv1 being at a low level. The inactive write circuit W] has no substantial influence on the potentials of the common data lines I) and D.
is placed in a high output impedance state to prevent

Similarly, the control signals φr, through φv4 are selectively set to high level corresponding to the memory array to be selected in the writing operation. Enable signal WE is set to low level and high level, respectively, and memory array selection signal is set to memory array M.
1, in other words, if a data read operation and selection of memory array M1 is instructed, the level is set to high level accordingly.

The read circuit RAI is activated by setting the control signal φr0 to high level, and the column switch C
-6 readout circuit RA for amplifying the data signal of the memory cell supplied via 5WI and the common data line and D;
The output signal of I is supplied to the data output terminal D out via the common signal line CST, 2 and the output buffer DOB. At this time, readout circuits RA2 to RA4
is kept in an inactive state and does not affect the signal level output from the read circuit RAI to the common signal line C3L2.

Similarly, control signals φr2 to φr are selectively set to high level in response to a memory array selection signal in a read operation.

FIG. 3 shows another embodiment of the present invention, in which MO3FETQ9 and MOSFETQIO shown in FIG.
The cut-off MO8FETQ11 is interposed between the signal line 8'' and two amplifying inverters 14.
．． 15 is provided, which is different from the embodiment described in F.
Effects similar to those of the above embodiment can be obtained.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the Examples described above, and can be modified in various ways without departing from the gist thereof. For example, in the above embodiment, the case where the signal line 8 is fixed at a high level is explained, but the M
It is also possible to fix it at a low level by reversing the conductivity type of the OSFET. In addition, the inverter circuit of the above embodiment is 0M0 in order to reduce power consumption.
It is composed of 8 circuits, but the N-channel type M
Enhancement by OSFET! --, Enhancement
element) configuration and enhancement-depletion (
Enhancement-Depletion
) It is also possible to adopt various circuit configurations mainly based on the cut-off MOS FET Q
10 and level fixing MO5FETQ13 is MO8FE
It is possible to replace it with a switching element other than T.

〔effect〕

As is clear from the above explanation, the invention disclosed in this application provides the following effects.

(1) Since a level fixing switching element is provided that fixes the level of the signal line to high level or low level based on the control signal that indicates non-selection of signal transmission, the signal on the signal line and the control signal are input. It is possible to adopt a two-person type inverter circuit, and as a result,
The overall circuit configuration can be simplified.

(2) As a result of the simplification of the circuit configuration, the number of constituent elements is reduced, and the non-selected state of signal transmission can be achieved with high efficiency without delay.

[Application field]

In the above description, the invention made by the inventor of the present application was mainly applied to an SRAM device, which is the technical field behind the invention.

This is not limited to l) readout circuits such as RAM (dynamic random access memory) devices, and signal transmission devices such as input/output circuits that connect data bus lines of microcomputers and their built-in circuits. It is widely applicable7

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment in which a signal transmission device according to the present invention is applied to a readout circuit of an SRAM device, and FIG. 2 is a specific circuit diagram of a sense amplifier. FIG. 3 is a circuit diagram of another embodiment, and FIG. 4 is a circuit diagram showing a schematic configuration of an SRAM device. S A...Sense amplifier, 8...Signal line, Q9...
1st degree switch element (P-channel type MOSFET)
, QIO...second switch element (N-channel type M
OSFET), Qil...Third switch element (cutoff MO5FET), 12...Inverter circuit, Q1
3...Fourth switch element (MO3FET for level fixing)
), φri...Selection control signal. Agent: Patent attorney Katsuo Ogawa (′−゛−). Figure 1 Figure 2

Claims (1)

[Claims] 1. A first switch element provided between one terminal of a power source and an output terminal and switch-controlled by an input signal;
a second switch element provided between the other terminal of the power source and the output terminal and controlled to be complementary to the first switch element; and a third switch element connected in series with the second switch element. and control means for forcing the level of the input signal to turn off the first switch element and turn off the third switch element based on the control signal. Device. 2. The control means includes a control line coupled to the input terminal of the third switch element, and a fourth switch element that is switch-controlled based on the control signal to force the level of the input signal to a predetermined level. A signal transmission device according to claim 1, characterized in that the signal transmission device comprises: 3. The first and fourth switch elements are M of the first conductivity type.
3. The signal transmission device according to claim 2, wherein the signal transmission device is made of an OSFET, and the second and third switching elements are made of a second conductivity type MOSFET. 4. The signal transmission device according to claim 1, wherein the input signal is generated by a sense amplifier provided in a memory mat.