JPH01204294A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To cause power consumption to be low by turning-on and off a switching means, which is provided in the power source supplying route of an inverter in an output step, and adjusting a through current period to flow between the power source of the output inverter and a GND. CONSTITUTION:An n-MOST 12 to constitute an inverter 10 and an n-MOST 16, which is a transistor for through current limit with a ground, are provided. When an H is inputted to the gate of an n-MOST 14 and an L is inputted to the gate of the n-MOST 16, the n-MOST 16 is turned off and a through current does not flow during the period. Next, when the L is inputted to the base of the n-MOST 14, the potential of a node 9 goes to be the H. Then, when an output is needed, the H is inputted to the gate of the n-MOST 16 and the n-MOST 16 is turned on. Then, the output is removed. Thus, a time, during which the trough current flows most, can be shortened and the energy consumption can be made the lowest.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a current type sense amplifier for a semiconductor memory.

[Prior Art] FIG. 4 is a circuit diagram showing a conventional current-type Hinsamplifier. In the figure, 1 is a sense amplifier, 2 is an inverter, and inverter 2 is a p-type MO8 transistor (hereinafter p-
MOS T) 3 and an 0111 MO3 transistor (hereinafter abbreviated as n-MO3T) 4. The output of inverter 92 is connected to the gates of n-MO3Ts 5 and 6.

The drain of the n-MO8T5 is connected to the high potential side, and the source is connected to the input of the inverter 2. When turned on, the potential of the node 7, which is the common connection point between the source and the input of the inverter 2, becomes "1-bi". Let's try.n-MO3T6
has a drain connected to the drain of p-MO3T8, and a source connected to node 7. And n-M OS
The common connection point of the drains of -r6 and p-MO3T8 is designated as node 9. The gates of the p-vosTs are grounded, and the sources are connected to the high potential side.

Reference numeral 10 denotes an output stage inverter consisting of p-MO8T11 and n-MO8T12, whose input is connected to node 9 and whose output is node 13.

14 is an n-MO8T connected in series to the bit line 15, and when the word line connected to the gate becomes 1'', it is a memory that stores 0'' or 1'' depending on whether it is turned on or not. One of seven cell groups is shown.

Next, the operation will be explained. When node 7 is L'', inverter 2 outputs H11, and this “11” is n-MO
Since the gates of 8T5 and 6 are manually operated, n-MO8T
5 and 6 are ONL, and the potential of node 7 is about to exceed °'II". However, the potential of node 7 is
When the potential exceeds the inversion potential of , inverter 2 outputs L'',
Since this "L" is input to the gates of n-MO3T5 and 6 and n-MO8T5 and 6 are turned off, the potential of node 7 does not exceed the inverted potential of inverter 2.

If the potential of node 7 becomes higher than the inverted potential of inverter 2, the bit line 15 and n-MO8T are connected from node 7 to
A current flows to the GND side through I4, and the potential of node 7 becomes low. This is because, of course, when the n-MO8T14 is ON, even when it is OFF, a slight current path is created on the GND side due to leakage current. Then, when the potential of the node 7 becomes low and becomes less than the inverted potential of the inverter 2, the inverter 2 outputs "tobi'".
l-1'' is n -M OS-r Game 1 of 5 and 6
Since the n-MO3Ts 5 and 6 are turned on, the potential of the node 7 does not become lower than the inverted potential of the inverter 2. In this way, the potential of node 7 is self-biased to approximately the inverted potential of inverter 2.

Then, when 'l-1' is input to the gate of n-MO8T14, n-MO3TI4 turns on, the potential of node 7 decreases, and n-MO3T6 becomes ONL, n-
MO8T6. Node 7, bit line 15 and n-MOS-
A current flows through r'14, and node 9, which is the input terminal of inverter 10, becomes "L", so that node 13, which is the output of inverter 10, becomes "'H".

On the other hand, when the n-MO8T14 is turned off by inputting L'' to the gate of the n-MO8T14, the potential of the node 7 rises, and the n-MO3T6 is turned off, so the input of the inverter 10 becomes 'H'. Inverter 10
The output of node 13 becomes 'L'.

[Problem to be solved by the invention]

The conventional current type sense amplifier is configured as described above, so when n-MO8TI 4 is turned on, n-MO8T
6 is also ONL, the potential of node 9, which is the input of inverter 10, becomes low. However, as mentioned above, since the potential of node 7 is self-biased to almost the inverted potential of inverter 2, the potential of node 9 also decreases only to about the inverted potential of inverter 2, ″
does not become completely O■. Therefore, the transistor 14
is ONL, ml- which constitutes the inverter 10
M08T12 is completely 0FFt! First, there is a problem in that a through current always flows between the power source of the inverter 10 and GND, resulting in large power consumption.

The present invention has been made to solve the above problem, and aims to provide a semiconductor integrated circuit device that reduces power consumption by limiting the period during which a through current flows.

[Means to solve the problem]

The semiconductor integrated circuit device according to the present invention has a first terminal that is held at a substantially constant potential by self-biasing, and an output stage inverter depending on whether a current of a certain value or more flows out from the first terminal. A semiconductor device comprising: a sense amplifier that outputs l-1" or °"l I+ through a memory cell; and a bit line to which a memory cell is connected and which allows a current path to flow through the memory cell depending on the memory content of the memory cell when reading information. In the integrated circuit device, a switching means is provided in a power supply path of the inverter in the output stage.

[Effect]

The switching means in this invention cuts the through current flowing between the power source of the inverter in the output stage and GN1 by turning off.

〔Example〕

FIG. 1 is a circuit diagram showing a current type sense amplifier in a semiconductor integrated circuit device which is an embodiment of the present invention.

In the figure, the difference from the conventional circuit shown in FIG. 4 is that an n-MO3T16, which is a through-current limiting transistor, is provided between the n-MO8T12 constituting the inverter 10 and the ground j11.

Other configurations are similar to the conventional circuit shown in FIG.

In the above configuration, the operation in which the node 7 is self-biased to approximately the inverting type of the inverter 20 is similar to the conventional circuit shown in FIG.

Next, n-MO81'1417) Explanation of the operation to limit the period of v4 current flowing to the inverter 10 when gate bias' or "L'° is input. 1J
Ru. "II" on the gate of n-MO8T14 like in the previous j-ho
” is input, n-MO8T14 turns ON, and the line 15 and n- MO8T6. to node 7 and pin 1 are
A current flows through MO3T14 and the potential of node 9 decreases. In this case, if °L'' is input to the gate of n-MO3T16, n-MO3T16 is 0FFL, and no through current flows during the above period. Next, n-MO3T1
When °L" is input to the base of node 4, the potential of node 9 becomes "l-1" as described above. Then, when an output is required (for example, when switching the latch in the output stage), n -fvlO
Input 'l-1' to the gate of 8T16, n-MOS
``Turn on r16 and take out the output 1!'' d)
If it is small, the length between 1111 and 1111 where the L1 flow is the shortest, and the lowest power consumption can be achieved. The period during which the through current is cut can be freely set according to the timing of the "L" and "L" signals input to the gate of the n-MO8T16.

FIG. 2 is a circuit diagram of another embodiment of the invention. The difference from the embodiment shown in FIG. 1 is that an n-MO8 17 is further connected to the output of the impark 10. n-M
When the gate ``l-'' of O3T14 is input, the voltage of node 9 (& will sound -L as shown in the previous example).In this case, if n-MO8r16 is not ON, n-MO8
The source of T12 is not grounded. Therefore, inverter 1
Node 13, which is the output of 0, is not completely at ground level. In this case, if a circuit whose input is the output of the inverter 10 is directly connected to the next stage, malfunctions may occur. Therefore, n-MO8T17 is provided, and when n-MO8TI6 is 0 to F, a signal is given to the gate so that n-MO8T17 is also 0FFF, and the output of inverter 10 is placed in a high impedance state, eliminating the influence on the next stage circuit. I decided to do it.

- [In the above embodiment, a single sense amplifier 1 is used, but in order to select the output power for the same word signal η for a memory cell, a plurality of sense amplifiers 1 may be used as shown in FIG. 3. In this case, one latch is provided on the protruding horn step.
The n-MO8T17 connected to the output terminal of the inverter 10 in the output stage of the sense amplifier 1 can be used as a filler for column selection.

Note that in the embodiment L, the sense amplifier 1 directly connects the bit line 1.
5, but the bit line 15 and sense amplifier 1
A similar effect can be achieved even when a transmission gate for bit line selection is provided between the two.

Furthermore, the same effect can be obtained by inserting n-MO3T16 on the high potential side.

Further, both or one of MO8T 16 and 17 may be formed of p-MO8T, and in this case, the same effects as in the above embodiment can be obtained.

Further, in the above embodiment, the sense amplifier 1 is composed of 0MO8, but the same effect can be obtained even if it is written with NMO3F.

It can also be applied to cases where various power cut transistors are used to reduce power consumption by cutting excess current between the transistors that make up the sense amplifier 1 and the amplifier or ground. The same effect can be obtained.

(Effects of the Invention) As described above, according to the present invention, a switching means is provided in the power supply path of the inverter in the output stage, and by switching this switch to 0N10FF, the current flows between the power supply of the output inverter and G N D. Since the current interval can be adjusted, it is possible to reduce the amount of dummy power in the semiconductor integrated circuit device.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a semiconductor integrated circuit device which is an embodiment of the present invention, Figs. 2 and 3 are circuit diagrams showing other embodiments of the invention, and Fig. 4 is a circuit diagram showing a conventional semiconductor integrated circuit device. It is a circuit diagram of a circuit device. In the figure, 1 is a sense amplifier, 7 is a node, 10 is an inverter, 14 is a memory cell, 15 is a bit/line, and 16 is a
is a current limiting transistor. Note that the arrows in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) It has a first terminal that is held at a substantially constant potential by self-biasing, and is set to "H" via the output stage inverter depending on whether a current of a certain value or more flows out from the first terminal.
Alternatively, in a semiconductor integrated circuit device comprising a sense amplifier that outputs "L" and a bit line to which a memory cell is connected and which allows a current path to flow through the memory cell depending on the storage content of the memory cell when reading information, the output A semiconductor integrated circuit device characterized in that a switching means is provided in a power supply path of an inverter in a stage.