JPS6298911A - Input buffer circuit - Google Patents

Abstract

PURPOSE:To make the entire current of the titled circuit nearly zero when an input signal of a power voltage level or so is given by providing the 1st control circuit controlling a current level of a constant current circuit and the 2nd control circuit inputting an input level signal and controlling the 1st control circuit. CONSTITUTION:When a signal VI1 is at the TTL level, since an effective voltage between a gate and a source of an element P4 is large, no effect is given to a control system comprising elements P3 and N4. When the level of the signal VI1 approaches a level VD1 gradually, since the capability of the element P4 is deteriorated, a current flowing to a control circuit system comprising the elements P3, N4 is suppressed, the potential at a point 5 is increased gradually and the potential difference between the points VD1 and 5 reaches a threshold voltage of the element P2 or below and a current of a constant current circuit comprising the elements P2, N2 and N3 is lost. On the other hand, the gate-source voltage of the element N1 is increased much larger, that is, since the capability of the element N1 is increased gradually, the level of a point Vo1 is drawn to a common potential VS1. Thus, when a power voltage level is given to the input, the current consumption is made nearly zero.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input buffer circuit used in a semiconductor device such as a semiconductor memory.

[Summary of the invention]

The present invention relates to a detection circuit in an input buffer circuit used in a semiconductor device such as a semiconductor memory.

It consists of a constant current circuit and two control circuits, a first and a second control circuit.Even if the power supply voltage fluctuates, the current level of the constant current circuit is kept constant by the first control circuit, and when the input signal is the power supply voltage, By suppressing the current level of the constant current circuit by the second control circuit, the current consumption is zero when the input signal is at the power supply voltage, and the logic level is kept constant even if the power supply voltage fluctuates. be.

[Conventional technology]

FIG. 2 shows a conventional input buffer circuit. In the diagram, V-engine 1
1 is an input signal, VOll is an output signal, VDll is a power supply voltage, VSl1 is a ground potential, P'11, PI3. PI3
is a P-channel type M10S transistor, N11, N1
2. N13. , N14 is an N-channel type MO8) transistor, and 11.12°, 13.14.15 are respective nodes.

V engineering 11 is T T L (Transistor Tr
ansistorLogic) signal, the low potential side (α
The operation of the circuit system will be explained by taking as an example the case where the potential changes from 8V) (hereinafter referred to as "H") to a high potential side (2, 2V) (hereinafter referred to as "H"). FIG. 5 shows potential changes at each node in this case. Each numerical value in FIG. 5 corresponds to each numerical value in FIG. 2, the horizontal axis is time T1, the vertical axis is voltage VSVD11 is the power supply voltage, vGL
is at the logic level.

When Vllll is L, the gate potential of Ni1 of the detection circuit (consisting of Pll and N11) and its threshold voltage are close to each other, so the current flowing through the entire circuit system is small.

The current flowing through the constant current circuit composed of Pl 2 , N13, and N12 is also small, and the drain potential 14 of 212, which is the current source of this circuit, has a value close to VDl 1.

At potential 15, the current flowing through the circuit system is small, so N
The potential is lower than the potential of 14 by the threshold voltage of 13. On the other hand, the potential of the output terminal 12 is at almost the same level as the potential of the output terminal 13 because the gate-source voltage of Pll of the detection circuit is large.

The potential of the output terminal 15 of the control circuit consisting of P13 and N14 is set in such a way that a relationship such as βN14 is established between the transistor coefficient βP14 of P15 and the transistor gain coefficient βN14 of N14, so that VDll
located at a level close to

■As T11 rises from B, the current capacity of Nli increases, so the drain-source voltage of Pl2 and the gate-source voltage of N15 increase, i.e. 14.1
3, each potential gradually decreases.

Further, the potential of 12 also gradually decreases because the gate-source voltage of Pll decreases.

When VT11 becomes near VGL, the potential of 15 and VDll
The value obtained by subtracting the threshold voltage of Pl2 from the difference value of VDl
The difference value between the potentials of l and 14 is larger, that is, Pl
2 is in the saturation region (the value of this current flowing to the detection circuit consisting of Pll and N11 is uniquely determined by the potential of 15), and the reduction rate of 12 is also large.

When VT11 further increases, the current level of the entire circuit drops again, so the potential at 14.13 begins to rise again, and Pl2 enters the unsaturated region again.

As mentioned above, when comparing the transistor gain coefficients of P13 and N14, P13 is much larger, so the amount of change in the potential of 15 when the power supply voltage changes is small.

When Vlll is near VGL, f7) The difference value between VDll and potential 14 naturally changes depending on fluctuations in the power supply voltage, but if the value is always larger than the difference value between potential 15 and VDll described above, the logic level of this circuit is VGL. is the power supply voltage VD1
This means that it does not depend on 1.

Additionally, since the circuit is built in a differential system, it is resistant to manufacturing variations and noise.

[Problem that the invention seeks to solve]

Normally, when a semiconductor device is externally supplied with a chip enable signal that controls the selected/unselected state of the semiconductor device and is at the same level as the power supply voltage level of the semiconductor device, the current consumption of the semiconductor device is almost zero. becomes.

In the case of a semiconductor device that has the circuit described here as an input buffer circuit for a chip enable signal, even if a circuit with the same level of power supply voltage as the semiconductor device is supplied as a chip enable signal from the outside, the input buffer circuit is already The disadvantage is that current flows in the control circuit section (the circuit consisting of Pl3 and N14 in FIG. 2) and does not become zero.

The present invention provides an input buffer circuit that automatically reduces the current consumption of the circuit when a level equivalent to the power supply voltage is supplied as an input.The 10th level does not depend on the power supply voltage and is resistant to manufacturing variations and noise. The purpose is to

[Means for solving problems]

In order to solve the above problems, the present invention, as shown in FIG.
3) It consists of a transistor.

[Effect]

In the input buffer circuit (shown in Figure 1) configured as described above, when an input signal of about the power supply voltage level is input, T4 cuts off the current bus of the control circuit consisting of PS and N4, so the circuit The current as a whole becomes almost zero.

〔Example〕

An embodiment of the invention is shown in FIG. In the figure, Pl, T
2. PS, T4 is a P-channel type MOS transistor,
Nl, N2. N3. N4 is an N-channel MOS) transistor, VT1 is an input signal, v'7o1 is an output signal,
VDl is power supply ii! pressure, vsl is the ground potential, and 1 to 5 are each node.

When VT1 is TTL, the effective voltage between the gate and source of T4 is large, so it does not affect the control system consisting of PS and N4. Therefore, the operation of the circuit system in this case is as explained in the conventional section.

When VT1 gradually approaches VDI, the performance of T4 decreases, so PS and N4
The current flowing through the control circuit system consisting of T2, N2, and IJ3 is suppressed, and the potential of 5 gradually rises until the potential difference between VDl and 5 becomes less than the threshold voltage of T2, and the constant current circuit consisting of T2, N2, and IJ3. The current disappears, while the gate of N1 -
As the source-to-source voltage becomes larger, that is, the capability of N1 gradually increases, Vτ1 is pulled toward the ground potential vs1.

As explained above, by providing a P-channel type M'''6S transistor P4 with its gate connected to the input signal V1 between PS and N4, the circuit current is reduced when the power supply voltage level is applied to the input. It can be reduced to almost zero.

〔Effect of the invention〕

As described above, the input buffer circuit of the present invention is effective in that the current consumption becomes almost zero when the power supply voltage level is applied to the input.

[Brief explanation of drawings]

FIG. 1 is an input buffer circuit diagram according to the present invention, in which Pi,
T2, ps, T4...P channel type MO
9) Transistors N1, N2. N3. N4... N-channel MOS transistor VT1... Input signal vol... Output signal VDl... Power supply voltage vsl... Ground potential 1t 2 + 3 z 4 e 5... Each node in Figure 2 is a conventional input buffer circuit diagram, with Pll, Pl2
．． Pl3...P channel type MOS) transistors N11, N12. NIB, N14...N-channel type M'''6S transistor VT11...Input signal vol...Output signal VDll...Power supply voltage YSl 1...・・Ground potential 11.12, 13, 14.15・・・・・・Each node 3rd
The figure is an operating waveform diagram showing potential changes at each node in the figure when VT11 of the circuit in Figure 2 rises from L to H. The horizontal axis is time T1, the vertical axis is voltage ■, and vDll is The power supply voltage, VGL, is at a logic level. that's all

Claims (1)

[Claims] a detection circuit for detecting an input level signal; a constant current circuit for flowing a constant current into the detection circuit; a first control circuit for controlling the current level of the constant current circuit; An input buffer circuit comprising a second control circuit that controls a first control circuit.