JPS6298669A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce leakage currents at the OFF time of an MISFET by making the film thickness of a channel region thinner than source-drain regions. CONSTITUTION:A gate electrode 14 is formed on a channel region 12 and source- drain regions 11. The film thickness of the gate electrode 14 extends over approximately 2,000-3,000Angstrom . A section between the gate electrode 14 and the channel region 12 is insulated by a gate insulating film 13, and a section between the source-drain regions 11 is insulated by an insulating film 15 consisting of an silicon oxide film. The film thickness of the gate insulating film 13 extends over approximately 500Angstrom and the film thickness of the insulating film 15 over approximately 1,000Angstrom .

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and particularly to an active element of a semiconductor integrated circuit device.

[Background Art] It is conceivable to further configure a second MISFET on the first MISFET configured on the surface of the sP conductor substrate. The source and train regions of this second Ml5FET may be formed by introducing impurities into predetermined portions of a polycrystalline silicon layer formed on a semiconductor substrate. Further, the channel region of the second MTS["ET may be formed by providing a region into which impurities are not introduced between the source and drain regions.

The inventor of the present invention investigated the second Ml5FET and found that the channel region has the same film thickness as the source and drain regions, resulting in an increase in leakage current in a non-conducting state.

Note that a technique for forming the source and drain regions of MISFE from polycrystalline silicon layers is described, for example, in Japanese Patent Application No. 152998/1982.

[Object of the Invention] An object of the present invention is to provide a technique for improving the electrical characteristics of a MISFET.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

In other words, the source and drain regions of the MTSFET are cut off.
The channel region is composed of a conductive layer on a film, and the conductive layer is thinner than the conductive layer which is the source and train region.

The configuration of the present invention will be explained below along with examples.

[Example of large Iβ1] Figure 1 shows a first MISFET in which the source, drain region, and channel region are formed on the surface of a semiconductor substrate, and this first MISFET.
FIG. 2 is a plan view showing only the second Ml5FET of FIG. 1, and FIG. It is a sectional view taken along the line A-Δ in the figure. Incidentally, in FIGS. 1 and 2, insulating films other than the field insulating film are not shown in order to make the structures of the first and second Ml5FETs easier to see.

1 to 3, a field insulating film 2 made of a silicon oxide film is provided on the surface of a semiconductor substrate 1 made of P-type single crystal silicon.
A p-type channel stopper region 3 is provided on the surface of the substrate 1 below.

In this example, the first MISFET is configured on the surface of the substrate l, and the second MISFET is configured on the first MISFET.
It constitutes T. The first MISFET has an n° type semiconductor region 4, which is a source and drain region on the surface of the substrate 1. It is composed of a gate insulating film 5 made of a silicon oxide film and a gate electrode 6 made of a polycrystalline silicon layer. Note that the gate electrode 6 is not limited to a polycrystalline silicon layer (Mo.

It may be formed of a high melting point gold a film such as W, Ta, Ti, etc. or a silicide film of the above high melting point metal. moreover.

It may be a two-layer film in which the high-melting point all-reflective film or silicide film is provided on a polycrystalline silicon layer. A conductive layer 7 made of an aluminum layer is connected to the rl' type semiconductor region 4 which is a source and drain region through a contact hole 8 . The conductive layer 7 is insulated from the layers 1 to 6 by an insulating film 9 made of phosphosilicate glass (PSG) or the like. The conductive layer 7 is covered with an insulating film 10 made of PSG, a silicon nitride film, or the like.

In this embodiment, a first Ml5F formed on the surface of the substrate 1 is used.
Configure the second Ml5FET on E'r(7). The second Ml5FET has a source and drain region 11. made of an n'-type polycrystalline silicon layer. A channel region 12 made of a polycrystalline silicon layer into which no impurities have been introduced to reduce resistance, a gate insulating film 13 made of a silicon oxide film, and a gate made of a polycrystalline silicon layer? 1H414. The gate electrode 14 is provided on the channel region 12 and the source and drain regions 11 . The film thickness of the gate electrode 14 is approximately 2000 to 3000 [λ]. The gate electrode 14 and the channel region 12 are insulated by a gate insulating film 13.

It is insulated from the drain region 11 by an insulating film 15 made of a silicon oxide film. Gate insulation 11J13
The film thickness of the insulating film 15 is about 500 [λ], and the film thickness of the insulating film 15 is about 1000 [λ]. Gate electrode 1 of this example
4 is long in the channel length direction as shown in FIG. 2, but the length is not limited to 4t. The channel region 12 is formed as a long planar pattern in a direction intersecting the channel length direction.
It may be placed on top of the . In this case, the pattern is such that the sides of the gate electrode 14 extend over the ends of the source region 11 and the drain region 11 . The source and train regions 11 are insulating films l
It is provided above the gate electrode 14, and is mainly located directly below the gate electrode 14. The portion of the polycrystalline silicon layer other than the portion under the gate electrode 14 is mainly used as wiring. That is,
The source and drain regions 11 and the portion used as wiring are made of the same polycrystalline silicon layer and are integrally formed. The thickness of the polycrystalline silicon layer used as the source/drain region 11 and the wiring integral therewith is approximately 2000 to 3000 [λ]. The channel region 12 is the source on the insulating film 10 and the source is between the drain region 11.

It is formed integrally with the drain region 11, and its width,
That is, the width in the direction intersecting the channel length direction is approximately the same as that of the gate electrode 14. The thickness of the channel region 12 is +1000 cλ]p1. degree. Note that since the gate insulating film 13 is provided on the L plane and side surfaces of the channel region 12, its planar pattern is the same as that of the channel region 12. That is, the length of the goo 1-insulating film 13 is approximately the same as the length between the source and drain regions 11 in the channel length direction, and is approximately the same as the width of the gate electrode 14 in the direction intersecting the channel length direction.

As described above, by making the film thickness of the channel region 12 thinner than that of the source and drain regions 11, the leakage current flowing through the channel region 12 is reduced, so that M I S
It is possible to improve the electrical characteristics of the FET.

A conductive layer 16 made of 13 layers of aluminum is connected to the source and drain regions 11 through a connection hole 17 . Similarly, the gap 11 between the conductive layer 16 and the electrode 14 is insulated by an insulating layer 18 made of PSG or the like. The thickness of the insulating film 18 is approximately 6,000 to 8,000 mm.

Next, mainly the second Ml5FET, that is, the source;
A method of manufacturing an MISFET in which the drain region 11 and channel region 12 are formed of polycrystalline silicon layers will be described.

4 to 10 show the second M in the manufacturing process.
It is a top view or sectional view of ISFET.

As shown in FIG. 4, a field insulating film 2 is formed on a substrate 1 by a well-known technique. P-type channel stopper region 3, rl'-type semiconductor region 4, which is a source and drain region. Goo 1
- Absolute g (membrane 5. gate 1 to electrode 6. conductive layer 7, connection hole 8,
An insulating film 9 and an insulating film 10 are formed. Note that this board 1
The MISFET formed in 1 and the conductive layer 7 connected thereto are not shown in the plan view used in the following description.

Next, as shown in FIGS. 5 and 6, a polycrystalline silicon layer 19 is formed on the entire surface of the insulating film 10 by, for example, CVD, and this polycrystalline silicon layer 19 is etched using a resist mask to form a source layer and a polycrystalline silicon layer 19. The drain region 11, its source, and the wiring integrated with the drain region 11 are patterned into a pattern. The etching mask is removed after etching. Note that an n-type impurity such as phosphorus is introduced into the polycrystalline silicon layer 19 by, for example, ion implantation. Further, the pattern of the polycrystalline silicon layer 19 is formed to be larger than the final pattern of the source and drain regions 11 and wiring, that is, the pattern at the end of the TXJ fabrication process.

This is because patterning is performed again by etching to form the channel region 12 in yt. However, since the distance between the source region 11 and the drain region 11, that is, the channel length, will not be changed by subsequent etching, it is set to a predetermined length during the patterning.

Next, as shown in FIG. 7, polycrystalline silicon p! is applied to the entire area on the substrate 1 by, for example, CVD. J20 to 1000 [A
] Formed to a film thickness of approximately . This polycrystalline silicic layer 20 is
Since this will become the channel region 12 later, no impurity is introduced in this step to lower the resistance. However, a trace amount of p- or n-type impurity may be introduced to adjust the threshold voltage of the MTSFET.

Next, as shown in FIG. 8, a resist mask 21 is formed on the polycrystalline silicon layer 20 formed previously. This resist mask 21 forms a pattern of source and drain regions 11 and interconnections on the upper part of the lower polycrystalline silicon layer 19, and a channel region 1 of the upper polycrystalline silicon layer 20.
The pattern of the channel region 12 is formed above the portion 2. Note that the width of the channel region 12 in the direction crossing the channel length direction is the width of the gate electrode 14.
Considering the mask alignment margin during formation,
The mask alignment margin is made larger than the width of 4. Next, after etching the portion exposed from the resist mask 21, the resist mask 21 is removed.

Next, as shown in FIG. 9, n-type impurities are diffused from the lower polycrystalline silicon layer N19 into the upper polycrystalline silicon layer 20 by annealing. Upper layer polycrystalline silicon M2
No n-type impurity is introduced into the portion that is the zero channel region 12, and n-type impurity is introduced into the other portions.

That is, channel region 12 is completed through this annealing step.

Next, as shown in FIG. 10, source and drain regions 1
1 and the exposed surfaces of the wiring formed integrally therewith are oxidized to form an insulating film 15, and the exposed surfaces of the channel region 12 are oxidized to form a gate insulating film 13. 5ELOC5 oxidation. Thereafter, a polycrystalline silicon layer is formed on the substrate 1 by, for example, CVD, and the polycrystalline silicon WJ is patterned by etching using a resist mask to form the gate electrode 14.

The resist mask is removed after etching.

, 1. An n-type impurity 1, such as phosphorus, is introduced into the gate electrode 14 by ion implantation or the like to lower the resistance. Next, the insulating film 18 is formed using, for example, PSG by CVD. Next, the insulating film 18 is selectively removed by etching using a resist mask to form a connection hole 17. The resist mask is removed after etching. Next, an aluminum layer is formed on the entire surface of the substrate 1 by sputtering, for example, and this aluminum layer is patterned by etching using a resist mask to form a conductive layer 16.
form. The etching mask is removed after etching. The next figure is not shown.

As a final protective layer, for example by CVD I) S G
.

Layer a silicon nitride film or the like.

[Effects] According to the new technology disclosed in the present application, the following effects can be obtained.

(1) In a MISFET in which the source, drain region, and channel region are formed using a conductive layer, the cross-sectional area of the cha is reduced, so that leakage current when the MISFET is non-conductive can be reduced.

(2) According to (1) above, it is possible to improve the electrical reliability of a semiconductor integrated circuit device including the MISFET.

(3) By making the conductive layer for forming the source and drain regions different from the conductive layer for forming the channel region, even if the thickness of the channel region is thin, the source and drain regions
Since the film thicknesses of the drain region and wiring can be increased, the resistance values of the source, drain region, and wiring can be reduced.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 show MIS FE of one embodiment of the present invention.
A plan view of T, FIG. 3 is a sectional view taken along the line AA in FIG. 1. 4 to 10 are plan views or cross-sectional views of the MISFET manufacturing process. 1. Substrate, 2. Field insulating film, 3. Channel stopper region, 4. Semiconductor region, 5.13.
...Gate insulating film, 6.14...Gate electrode, 7.1
6... Conductive layer, 8, 17... Connection hole, 9.10.1
5.18... Insulating film, 11... Source, drain region, 12... Channel region, 19.20... Polycrystalline silicon layer. 21...Resist mask. k Figure 3 Figure 4 Pit Figure 6 Figure 7 Figure 8 Figure 9 Figure 101

Claims (1)

[Claims] 1. Source and drain regions are spaced apart on a semiconductor substrate.
a MISFET comprising two first conductive layers, a channel region provided between the two spaced apart first conductive layers, and a second conductive layer thinner than the first conductive layer; Integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the first conductive layer and the second conductive layer are polycrystalline silicon layers. 3. The semiconductor integrated circuit according to claim 1, wherein the gate electrode of the MISFET is comprised of a third conductive layer provided on a gate insulating film on a second conductive layer which is a channel region. circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein no impurity is introduced into the second conductive layer, which is the channel region, for lowering the resistance.