JPS6298345U - - Google Patents
Info
- Publication number
- JPS6298345U JPS6298345U JP19120285U JP19120285U JPS6298345U JP S6298345 U JPS6298345 U JP S6298345U JP 19120285 U JP19120285 U JP 19120285U JP 19120285 U JP19120285 U JP 19120285U JP S6298345 U JPS6298345 U JP S6298345U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- signal
- detector
- circuit
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims description 2
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図は従来の位相同期回路のブロツク図であ
る。
図において、１はサンプリング位相検波器、２
はインパルス発生部、３はミクサ部、４はループ
フイルタ、５は電圧制御発振器、６は電圧比較回
路、７は分配器、８は検波器、９は増幅器、１０
はオフセツト補償用バイアス回路である。
FIG. 1 is a block diagram showing an embodiment of this invention, and FIG. 2 is a block diagram of a conventional phase locked circuit. In the figure, 1 is a sampling phase detector, 2
3 is an impulse generator, 3 is a mixer, 4 is a loop filter, 5 is a voltage controlled oscillator, 6 is a voltage comparison circuit, 7 is a distributor, 8 is a detector, 9 is an amplifier, 10
is an offset compensation bias circuit.
Claims (1)
発生するバランス型ミクサを有するサンプリング
位相検波器と、その位相誤差信号の増幅と高域雑
音除去及びオフセツト補正を行う比較回路付のル
ープフイルタと、その出力信号により位相比較信
号を発生する電圧制御発振器とで構成される位相
同期回路において、基準信号の分配器と、分配さ
れた信号のレベルを検波する検波器と、その検波
器の出力計増幅する増幅器と、その増幅器の出力
信号をもとに位相検波器のダイオードにバイアス
を加えるためのバイアス回路とを備えたことを特
徴とする位相同期回路。 A sampling phase detector having a balanced mixer that generates a phase error signal from a reference signal and a phase comparison signal, a loop filter with a comparison circuit that amplifies the phase error signal, removes high-frequency noise, and performs offset correction; In a phase-locked circuit consisting of a voltage-controlled oscillator that generates a phase comparison signal using an output signal, there is a reference signal divider, a detector that detects the level of the distributed signal, and amplification of the output of the detector. A phase locked circuit comprising an amplifier and a bias circuit for applying a bias to a diode of a phase detector based on an output signal of the amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19120285U JPS6298345U (en) | 1985-12-12 | 1985-12-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19120285U JPS6298345U (en) | 1985-12-12 | 1985-12-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6298345U true JPS6298345U (en) | 1987-06-23 |
Family
ID=31145124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19120285U Pending JPS6298345U (en) | 1985-12-12 | 1985-12-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6298345U (en) |
-
1985
- 1985-12-12 JP JP19120285U patent/JPS6298345U/ja active Pending