JPS629730Y2 - - Google Patents

Info

Publication number
JPS629730Y2
JPS629730Y2 JP11800882U JP11800882U JPS629730Y2 JP S629730 Y2 JPS629730 Y2 JP S629730Y2 JP 11800882 U JP11800882 U JP 11800882U JP 11800882 U JP11800882 U JP 11800882U JP S629730 Y2 JPS629730 Y2 JP S629730Y2
Authority
JP
Japan
Prior art keywords
sealing
integrated circuit
hybrid integrated
sealing lid
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11800882U
Other languages
Japanese (ja)
Other versions
JPS5923744U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11800882U priority Critical patent/JPS5923744U/en
Publication of JPS5923744U publication Critical patent/JPS5923744U/en
Application granted granted Critical
Publication of JPS629730Y2 publication Critical patent/JPS629730Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 (イ) 技術分野 本考案は混成集積回路の封止構造に関する。[Detailed explanation of the idea] (b) Technical field The present invention relates to a sealing structure for a hybrid integrated circuit.

(ロ) 背景技術 従来、混成集積回路の封止構造は第1図に示
す如く、所望の回路素子例えばチツプコンデン
サー1、モノリシツク集積回路2およびヒート
シンク3上にパワートランジスタ4を付着した
混成集積回路基板5に接着樹脂6により封止蓋
7を接着して封止していた。
(B) Background Art Conventionally, the sealing structure of a hybrid integrated circuit is as shown in FIG. A sealing lid 7 was adhered to and sealed with adhesive resin 6 to 5.

斯る構造では特に良好な封止を求められる発
熱を伴うパワートランジスタ4はシリコンレジ
ン層8を塗布して封止している。しかしながら
斯る封止構造では接着樹脂6の加熱硬化時に内
部で発生するガス等により小さい孔ができるお
それがあり、特にパワートランジスタ4の封止
を完全に行なえない欠点があつた。
In such a structure, the power transistor 4, which generates heat and requires particularly good sealing, is sealed by applying a silicone resin layer 8. However, in such a sealing structure, there is a risk that small holes may be formed due to gas generated inside when the adhesive resin 6 is heated and hardened, and there is a particular drawback that the power transistor 4 cannot be completely sealed.

(ハ) 考案の開示 本考案は斯る欠点を完全に除去する混成集積
回路の封止構造を実現するものであり、封止蓋
17と一体に隔離壁18を設け選択的にパワー
半導体素子のみ完全な樹脂封止を行うことを特
徴とする。
(c) Disclosure of the invention The present invention realizes a sealing structure for a hybrid integrated circuit that completely eliminates such drawbacks, and a separation wall 18 is provided integrally with a sealing lid 17 to selectively seal only the power semiconductor element. It is characterized by complete resin sealing.

(ニ) 考案の最良の実施例 アルミニウム、セラミツクス等の混成集積回
路基板15上に所望のパターンを有する導電路
上に所望の回路素子例えばチツプコンデンサー
11、モノリシツク集積回路12およびヒート
シンク13上にパワートランジスタ14を付着
する。本考案の特徴は封止蓋17にある。封止
蓋17は熱可塑性樹脂例えばテトロン系の
FRPET(商品名)を予じめ整形したものであ
る、封止蓋17の端部は基板15の周端と当接
し且つ接着樹脂16により接着される。なお封
止蓋17には一体整形により隔離壁18をパワ
ートランジスタ14を囲み且つ基板15に達す
る様に形成している。この隔離壁18と基板1
5とで他の回路素子と完全に区分された隔離室
19が形成される。この隔離室19には封止蓋
17の接着後、封止蓋17の上面に設けた孔か
らエポキシ樹脂等の封止樹脂20を充填する。
(d) Best Embodiment of the Invention Desired circuit elements such as a chip capacitor 11, a monolithic integrated circuit 12, and a power transistor 14 are placed on a heat sink 13 on a conductive path having a desired pattern on a hybrid integrated circuit board 15 made of aluminum, ceramics, etc. Attach. The feature of the present invention is the sealing lid 17. The sealing lid 17 is made of thermoplastic resin, such as Tetoron-based resin.
The end of the sealing lid 17, which is made of FRPET (trade name) that has been shaped in advance, comes into contact with the peripheral end of the substrate 15 and is bonded with adhesive resin 16. A separation wall 18 is formed on the sealing lid 17 by integral shaping so as to surround the power transistor 14 and reach the substrate 15. This isolation wall 18 and the substrate 1
5 forms an isolation chamber 19 completely separated from other circuit elements. After the sealing lid 17 is attached to the isolation chamber 19, a sealing resin 20 such as epoxy resin is filled into the isolation chamber 19 through a hole provided on the upper surface of the sealing lid 17.

従つて本考案の封止構造では、特に良好な封
止を求められるパワートランジスタ14を完全
にエポキシ樹脂等で完全に樹脂封止を実現でき
る。
Therefore, in the sealing structure of the present invention, it is possible to completely seal the power transistor 14, which requires particularly good sealing, with an epoxy resin or the like.

(ホ) 本考案の効果 本考案に依れば従来の簡易な封止構造で良い
回路素子は従来のまま、良好な封止を求められ
るパワートランジスタ等は本考案により選択的
に完全な樹脂モールドを行なえる。この結果発
熱を伴うパワー半導体素子の信頼性が大巾に向
上でき、且つ混成集積回路へのペレツトでの組
込みを可能にできる。
(e) Effects of the present invention According to the present invention, circuit elements that can be easily sealed using the conventional simple sealing structure can be left as they are, while power transistors, etc. that require good sealing can be selectively molded using a complete resin mold. can be done. As a result, the reliability of power semiconductor elements that generate heat can be greatly improved, and it is possible to incorporate them into hybrid integrated circuits in the form of pellets.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を説明する断面図、第2図は本
考案を説明する断面図である。 主な図番の説明、14はパワートランジスタ、
15は混成集積回路基板、17は封止蓋、18は
隔離壁、19は隔離室、20は封止樹脂、21は
外部リードである。
FIG. 1 is a sectional view illustrating a conventional example, and FIG. 2 is a sectional view illustrating the present invention. Explanation of main figure numbers, 14 is a power transistor,
15 is a hybrid integrated circuit board, 17 is a sealing lid, 18 is an isolation wall, 19 is an isolation chamber, 20 is a sealing resin, and 21 is an external lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 混成集積回路基板上にパワー半導体素子および
他の回路素子を設け封止蓋を用いて封止を行う混
成集積回路に於いて、前記パワー半導体素子を囲
む様に前記封止蓋と一体に隔離壁を設け、該隔離
壁と前記基板で形成される隔離室内に封止樹脂を
充填することを特徴とする混成集積回路の封止構
造。
In a hybrid integrated circuit in which a power semiconductor element and other circuit elements are provided on a hybrid integrated circuit board and sealed using a sealing lid, an isolation wall is provided integrally with the sealing lid so as to surround the power semiconductor element. A sealing structure for a hybrid integrated circuit, characterized in that an isolation chamber formed by the isolation wall and the substrate is filled with a sealing resin.
JP11800882U 1982-08-02 1982-08-02 Sealing structure of hybrid integrated circuit Granted JPS5923744U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11800882U JPS5923744U (en) 1982-08-02 1982-08-02 Sealing structure of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11800882U JPS5923744U (en) 1982-08-02 1982-08-02 Sealing structure of hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS5923744U JPS5923744U (en) 1984-02-14
JPS629730Y2 true JPS629730Y2 (en) 1987-03-06

Family

ID=30271420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11800882U Granted JPS5923744U (en) 1982-08-02 1982-08-02 Sealing structure of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5923744U (en)

Also Published As

Publication number Publication date
JPS5923744U (en) 1984-02-14

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