JPS6295974A - Multiplexed pwm inverter - Google Patents

Abstract

PURPOSE:To eliminate the 11th and 13th high frequency components, by forming the central phase of a PWM waveform to be the waveform of pulse with a specified electrical angle. CONSTITUTION:By a multiplexed inverter, DC power is converted to the AC power of a PWM waveform, and outputs with phase difference is synthesized by a transformer, and sine wave AC output is obtained via a higher frequency filter. The control circuit of the inverter is organized with a clock generation circuit 11, an up-down counter 12, an up-down changeover logic 13, a D/A converter 14, a comparator 15, and a gate logic circuit 16. From the counter 12, counter output forming the carrier wave of the PWM inverter is obtained by the first and second clocks of the clock generating circuit 11, and is converted to the PWM waveform through the D/A converter 14 and the comparator 15. The output is distributed to the respective phases U-Z of the phase difference of 120 deg. by the logic circuit 16 so that the respective phases may be respectively arranged at 67.5 deg., 112.5 deg., 247.5 deg., and 292.5 deg.. Then, the 11th and the 13th higher harmonic components can be made smallest.

Description

[Detailed description of the invention] A. Industrial application field The present invention relates to a multiplexed PWM inverter.

B. Summary of the Invention The present invention provides outputs of two pWM inverters with a phase difference of 3
In the multiplexed PW~1 inverter that is transformer-coupled with 0°, the center phase of the PWM waveform of each PWM inverter is set to 67
．． 5', 112.5°, 247.5' and 2925°
By using a single 5-pulse PWM waveform or a 5-pulse PWM waveform near the center phase, it is possible to reduce the 11th and 13th harmonics in the transformer output.

C1 Prior Art Conventionally, inverter multiplexing has been known as a method for reducing harmonics of an inverter output, and even when using a PWM inverter, multiplexing is used to further reduce harmonics.

FIG. 5 shows a conventional multiplexed PWM inverter.

PWM inverter 1.2 receives DC 1 from DC power supply 3.
Converts power into AC power with PWM waveform, and both outputs have a phase difference of 3
Synthesis is performed using an output transformer 4 with a 0° angle, and a sine wave AC output is obtained via a high-order harmonic filter 5.

The PWM waveforms of these two PWM inverters 1.2 have an electrical angle of 9
90°±30° centered on 0° support 270°, 270
Obtain 3 pulses with ゜-306 as the control interval, 0° to 60
°.

120° to 180° is fixed on, 180° to 240°,
300° to 360°: Fixed to Off. This PW
By setting the phase difference of both inverter outputs having M waveforms to 30 degrees, it is possible to make the fifth and seventh components of the harmonics of the composite voltage that have passed through the output transformer zero.

D Problems to be Solved by the Invention In the conventional multiplexing method using two PWM units, the combined output mainly contains the 11th and 13th harmonics, and the harmonic removal filter 5 is designed to obtain frequency characteristics that eliminate harmonics of the 11th order or higher. For this reason, the capacity of the filter 5 (other than the filter 5) becomes considerably large, which poses a problem that causes an increase in the size and cost of the device.

E Means and operation for solving the problems The present invention was made in view of the above problems, and is a multiplexed PWM inverter in which the outputs of two PWM inverters are transformer-coupled with a phase difference of 30°. In the converter, the center phase of the PWM waveform of each PWM inverter is approximately 67.5 degrees in electrical angle.
112.5', 247.5'', 5 pulse PWM waveform with 292.5°, equipped with f control circuit, 3
11th order generated by pulse.

Minimize the 13th harmonic acid content.

F. Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, and shows the main control circuit of the PWM inverter 1 or 2 in FIG. The clock generation circuit 1F is a crystal oscillation circuit 11. and PLL circuit 11. The two-stage frequency dividing circuits 11a and 114 provided in the closed loop of the PLL circuit 11□ generate a first clock CLK I and a second clock CLK2 obtained by dividing the first clock CLK I by [/n]. The up/down counter 12 uses the first clock CLKI as a counting input, and uses the second clock CLK2 as a preset input. The period of the second clock CLK2 is set by the frequency divider 113 to be 606 electrical angles of the basic basic circumference (output from the inverter), and
The period of the clock CLK1 is automatically set by the frequency divider 112 according to the number of digits of the counter 12 and the inverter output frequency control signal fc.

The counter [2] continues the counting of the first clock CLK1 from the preset value by the second clock CLK2 according to the up/down signal U/D to obtain a counting output that becomes the carrier wave (triangular wave) of the PWM inverter. As shown in the figure, the period of the triangular wave is 45°, and the apex is 75'', 30°, 5 in the range of 60° period of the second clock CLK2.
The preset value and up/down are switched so that the angle becomes 2.5°. This up/down switching signal U/D is generated by the up/down switching logic 13 from the output of the counter 12.

The counting output of the counter 12 is converted into a corresponding analog signal by the D/A converter 14, and this analog signal is compared with the output voltage control signal Vc of the PWM inverter in the comparator [5 and converted into a PWM waveform. be done. This PWM waveform is distributed by the gate knock circuit 16 with a phase difference of 120° to each phase.
It is extracted as a gate signal for each phase tJ, V, W, X, Y, and Z. When distributing the output of the comparator 15 to each phase, this gate logic circuit 16 sets the center of control of the PWM control signal (gate signal) at 67.5° for each phase.
112.5', 247.5', and 292.5'. In addition, each phase of 0° ~ 60'', 120° ~ 1
80° is fixed on, 180'~240°, 3006~
3600 is fixed to off so that the inverter output voltage can start from zero.

The output signals of each of these circuits are as shown in FIG. 2, the preset value of the triangular wave signal is 1/3 of its peak value, and the PWM waveform is a 5-pulse waveform. According to such PWM waveform generation, the center of control is set at 675°.
, 112.5°, 247.5°, and 292.5°, the triangular wave period is 45°, and while the configuration uses one up/down counter 12, the 11th and 13th harmonics are added to the inverter output. You can reduce it.

Theoretically, the angle at which the 11th and 13th harmonics are the smallest is slightly shifted from the above control center angle, and it also changes depending on the control rate of the inverter, but in practice, the angle at which the 11th and 13th harmonics are minimized is It comes small.

In addition, in the embodiment, a case was shown in which the desired triangular wave was obtained by the up/down counter 12 and the switching logic 13; however,
As shown in FIG.
The counter 17, which is reset at a cycle of 0°, obtains a counting ratio up to a predetermined value, and uses this counting output as address data.The write data of ROM 1g is written in the 0° to 60° range of the triangular wave signal shown in Fig. 2. It is possible to obtain the same effect by using a configuration in which the numerical value corresponds to the waveform of , and this numerical value is converted into a triangular wave analog signal by the D/A converter 14.

Triangular wave signal generation using such a ROM facilitates the processing of triangular waveforms, as shown in Figures 4 (a), (b), and (c).
).

As shown in (d), various complex waveforms can be obtained without the need for switching logic, and by slightly shifting the center of the control 1. It is also possible to minimize the 11th and 13th harmonics by obtaining a waveform. Note that the control center angles are 67.5' and 112.5° as described above due to the harmonic content.

2475°, plus or minus 1.5 from 292.5°
It is desirable to keep it within °.

Effects of the G8 Invention As described above, according to the present invention, the control range of each phase can be increased to 90
In order to create a control circuit that has four control circuits at the center of the PWM waveform in two multiplexed PW Xi inverters that are set at 30° and 270°±30°, and fixed on or off for other sections. , 1st and 13th harmonics are minimized, and the control circuit configuration has the effect of requiring a simple triangular wave generating means such as a counter and switching logic or ROM.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a main part circuit diagram showing another embodiment of the present invention, FIG. 4 is a waveform diagram of another triangular wave signal according to the present invention, and FIG. 5 is a circuit diagram of a multiplexed PWM inverter. , FIG. 6 is a conventional P W M waveform diagram. 1.2. PWM inverter, 4. Output transformer,
5. Harmonic removal filter, 11. Clock generation circuit, 12. Up-grain counter, ■3. Up-down switching ronok, 14. D/A converter, 15..Comparator, 16.. Gate knock circuit, 17..・Counter, 18... ROM Figure 5 Loaded PWM inverter / 10 Royama Figure 6 Conventional nPWM wave opening z@)

Claims (1)

[Claims] In a multiplexed PWM inverter in which the outputs of two PWM inverters are transformer-coupled with a phase difference of 30°,
The control circuit is equipped with a 5-pulse PWM waveform in which the center phase of the PWM waveform of each PWM inverter is approximately 67.5°, 112.5°, 247.5°, and 292.5° in electrical angle. Features of multiplexed PWM inverter.