JPH0757097B2 - Multiplexed current source inverter device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a multiplexed current source inverter device that outputs a sinusoidal alternating current by being subjected to pulse width modulation control.

[Background of the Invention]

A current source inverter is often used as an inverter that drives an AC motor. Current source inverters include those that output a rectangular wave current and those that output a sine wave current. Attention has been paid to the reason that a current source inverter that outputs a sine wave current is suitable for driving an AC motor because it can reduce harmonics.

The applicant has previously filed Japanese Patent Application No. 56-186816 (Japanese Patent Application Laid-Open No. 58-89073).
No.) has proposed a current source inverter that outputs a sinusoidal current.

This current source inverter connects the self-extinguishing element with a GREAT connection, connects the DC input side with a DC reactor for DC current smoothing, and absorbs the overvoltage generated at the AC output side during switching of the self-extinguishing element. The smoothing capacitor is connected. By the way, in order to put such a current source inverter into practical use, it is necessary to increase its capacity. Increasing the capacity of the inverter can be realized by increasing the capacity of the self-extinguishing element forming the inverter. The capacity of the self-extinguishing element can be increased by connecting the elements in series and parallel. However, the current value that each element must turn on or off increases as the inverter capacity increases. Therefore, the capacity of the smoothing capacitor provided for absorbing the overvoltage increases in proportion to the current side. Also,
In order to reduce the harmonics contained in the output current of the inverter and obtain a waveform close to a sine wave, the switching frequency of the self-extinguishing element must be increased. If the switching frequency is increased, the switching loss of the device will increase.
Since the switching loss increases as the capacity of the device increases, there is a limit to increase the switching frequency. Therefore, the sine wave output current contains many harmonics.

On the other hand, the capacity of the inverter device can be increased by connecting a plurality of inverters in parallel and multiplexing them. For example, as described in Japanese Examined Patent Publication No. 59-20270, there is a method in which the output terminals of two or more thyristor type current source inverters are connected in parallel and the ignition phases of the respective inverters are shifted. In the case of this method, the current of each current source inverter is a square wave current having a width of 120 degrees, so that the switching frequency of the switching element is constant regardless of the number of multiplexed units. However, the output current has a step-like shape due to the superposition of the square wave current. Therefore, the output current still contains many harmonics. In order to further reduce the harmonic component, more inverters have to be connected in parallel. Further, since the output current is stepwise, the harmonics cannot be sufficiently reduced.

[Object of the Invention]

An object of the present invention is to reduce the harmonics of a multiplexed current source inverter device and to downsize the device.

[Outline of Invention]

The present invention is provided with at least two inverters configured by Gratz connecting self-extinguishing elements, wherein the AC output side of each inverter is connected in parallel to the load to be connected, and the DC input side of each inverter is connected. The same polarity is connected to each other by AC reactors, and a main circuit section in which DC power is supplied from the midpoint of each AC reactor via a DC reactor, and an output frequency command that commands at least the output frequency of the inverter. Therefore, a PWM pattern generation circuit for generating a predetermined pulse width modulation pattern signal for each cycle, a pulse pattern control signal for turning on and off the self-extinguishing element of the in-phase arm of each inverter with the pulse width modulation pattern signal as an input A phase difference adding circuit that adds a phase difference to each other, and a phase difference is added between each inverter by the phase difference adding circuit. Characterized by comprising the said control circuit section comprising a gate circuit for driving the self-turn-off devices of each inverter on the basis of the control signal.

Example of Invention

FIG. 1 shows an embodiment of the present invention. FIG. 1 shows a duplicated example.

In FIG. 1, an inverter INV1 and an inverter INV2 are connected in parallel via AC reactors 3 and 4. The intermediate tap of the AC reactor 3 is connected to the positive side of the DC power supply 1 via the DC reactor 2, and the intermediate tap of the AC reactor 4 is connected to the negative side of the DC power supply 1. A load 5 and smoothing capacitors 6 to 8 are connected to the AC output terminals of INV1 and INV2 connected in parallel. The capacitors 6 to 8 absorb the surge voltage generated by the energy stored in the reactance component of the load 5 when the inverters INV1 and INV2 are switched. Inverters INV1 and INV2 are gate turn-off thyristors (hereinafter abbreviated as GTO) that are connected by GREATS
It is composed of 9-14 and 15-20. GTO 9 to 20 are gate signals U _P1 , V _P1 , W _P1 , U _N1 , V _N1 , W _N1 , U from the gate control circuit 21.
_P2 , V _P2 , W _P2 , U _N2 , V _N2 , W _N2 are supplied.

FIG. 2 shows an example configuration of the gate control circuit 21. In FIG. 2, the PWM pattern generation circuit 211 generates a PWM pattern signal P at a frequency according to the frequency command f ^* and adds it to the phase difference adding circuit 213. The phase difference adding circuit 213 has a pattern signal P.
An inverted PWM pattern signal obtained by inverting the signal from the NOT circuit 211 is also added. The PWM pattern signal P is preset so that the harmonic components are minimized. The phase difference adding circuit 213 outputs to the pattern P, pattern signals P ₁ , P ₂ , ₁ and ₂ having a phase difference based on the pattern signal P. Pattern signal P ₁
Is π / 6 ahead of P ₂ , and pattern signal ₁ is π above ₂
/ 6 Suppose it was delayed. These four pattern signals P ₁ , P ₁ ,
_The phase difference adding circuit 213, which forms a gate signal for one arm by a combination of ₂ and ₂ , generates only 48 pattern signals for 12 arms and adds them to the gate signal pattern synthesis circuit 214. The gate signal pattern synthesis circuit 214 includes gate signals U _P1 , V _P1,, W _P1,, U _N1 , V _N1 , W _N1 for the inverter INV1 and gate signals U _P2 , V _P2 , W _P2 , U _N2 , V for the inverter INV2. _N2 and W _N2 are created and added to the inverters INV1 and INV2 via the gate circuits 215 and 216, respectively.

FIG. 4 shows the relationship between the PWM pattern signals P ₁ , P ₂ , ₁ , ₂ and the gate signal. Fig. 4 shows the frequency of the inverter frequency A, B
Is divided into 24 equal parts and shown as periods 1 to 24. For example, U _P
Looking at the arm, in period A inverter INV1
Add P ₁ and ₂ to, and add IN ₂ to P _{2 and 1} . In the period B, on the contrary, P _{2 and 1} are added to INV1 and INV2 is
Add P ₁ and ₂ . The other arms V _P , W _P , U _N , V _N , and W _N have the same relationship although the phases are different.

PW for generating the gate signal in the relation of FIG. 4 in FIG.
Specific examples of the M pattern generation circuit 211, the phase difference addition circuit 213, and the pattern synthesis circuit 214 are shown. PWM pattern generator
211 is an oscillator 9 that oscillates at a frequency according to the frequency command f ^*
1, a counter 92, and a memory 93 that stores the PWM pattern signal P. In addition, the phase difference adding circuit 213 is 2
It is composed of a quaternary ring counter 94 and 48 AND circuits AND, and the gate signal pattern composition circuit 214 is composed of 12 OR circuits OR corresponding to the number of arms of two inverters. The clock signal generated by the oscillator 91 according to the inverter frequency command ^* is counted by the counter 92, and the count value is used as the input signal of the memory 93 and the 24-bit ring counter 94. The counter 92 is reset to zero after counting a fixed value. The 24-base ring counter outputs the distribution signals R _{1 to} R ₂₄ .

Gate signal applied to GTO9, 15 of inverters INV1, INV2
U _P1 and U _P2 are obtained by the following equation.

Gate signal U _P1 A period _{U P1 = P · R 1 +} R 2 + R 3 + R 4 + R 5 + · R 6 = R 1 + R 3 + R 4 + 2 B period _{U P1 = P · R 14 +} R 15 + R 16 + · R _{17 = R 2 + R 15 +} R 16 + 1 gate signal U _P1 A period _{U P2 = P · R 2 +} R 3 + R 4 + · R 5 = P 2 + R 3 + R 4 + 1 B period _{U P2 = P · R 13 +} R _{14 + R 15 + R 16 +} R 17 + · R 18 = P 1 + R 15 + R 16 + 2 gate signals U _P1 and to illustrate the relationship between the U _P2 is as Figure 5. The pattern signal P ₁ leads the pattern signal P ₂ by π / 6, and the pattern signal ₁ is delayed from the pattern signal ₂ by π / 6. Hereinafter, when the gate signals are obtained for the other arms in the same manner as in FIG. 4, the gate signals U _P1 , V _P1 , W _P1 , U _N1 , V _N1 , W _N1 , U shown in FIG. 6 are obtained. _P2 , V
_P2 , W _P2 , _UN2 , _VN2 , _WN2 are obtained. Fig. 6 shows the PWM control current waveforms i _IU , i _IV , i _IW and output current waveforms when the GTOs 9 to 20 are switched according to the gate signals thus obtained.
i _U , i _V , i _W are also shown. The periods 1 and 2 shown in FIG. 6 are enlarged and shown in FIG. The start point of period 1 is t ₀ , the gate signal
The time point when W _P1 changes to Low level and the gate signal U _P1 changes to High level is t ₁ , the time point when the signal W _P1 changes to High level and the signal U _P1 changes to Low level is t _2, and so on. ₃ ~
t ₁₀ The operation of the inverters INV1 and INV2 in each period is as shown in FIG. In Figure 8 (a), GTO11,
13, 17 and 19 are on, and the current I _d flows through loop 1 and loop 2. A half of the direct current I _d flows through each loop 1 and 2, and the U-phase PWM control current i _IU is zero. Next, GTO9
When turning on and turning off 11, the current I _d flows through loop 2 and loop 3 as shown in FIG. 8 (b). At this time, Becomes In the period 1 of FIG. 7, the following are shown in FIGS. 8 (a) and 8 (b).
Repeat the operation of. Next, in period 2, GTO15 at t ₆
Turns on and 17 turns off. The operating state is as shown in FIG. 8 (c), and the U-phase PWM control current i _IU becomes a current equal to the direct current I _d by superimposing the current I _d / 2 of the loop 3 and the loop 4. Hereinafter, in period 2, the operations of FIGS. 8B and 8C are repeated. The PWM control current i _IU in one cycle of the operating frequency of the inverter becomes a stepwise current as shown in FIG. Each GTO
The capacitors 6 to 8 provided to absorb the overvoltage generated during the switching of 9 to 20 have an effect as a filter. Therefore, the harmonic currents contained in the PWM control current i _IU are absorbed by the capacitors 6 to 8. Therefore, the output current i _U becomes almost a sine wave.

Although the sine wave current is output and supplied to the load 5 by performing the above operation, it is possible to make a sine wave without increasing the switching frequency and to reduce the capacity of the smoothing capacitors 6 to 8. Will be described with reference to.

In the embodiment of FIG. 1, as shown in FIG. 6, the number of pulses of the gate signal of each arm per cycle of the inverter operating frequency is set to 5 for simplification. In JP-A-58-89073 cited as the present invention and the prior art, PWM control current waveforms when the pulse number M of the PWM pattern is 5 are shown in FIGS. 9 (a) and 9 (b). 9 (a), (b)
Although the switching frequencies of the GTOs are equal, as is apparent from the figure, the waveform of the PWM control current i _IU becomes closer to a sine wave in the present invention shown in FIG. 9 (a). In order to make the conventional current i _IU shown in FIG. 9 (b) close to a sine wave to the same extent as in the present invention, according to the experimental results of the inventors, it was necessary to set M = 9. According to the experimental results, the switching frequency of GTO is almost double that of the present invention. This means that the switching frequency of each GTO can be reduced to 1/2 in the case of the present invention in order to obtain a waveform comparable to the current waveform i _IU obtained by the conventional method. Furthermore, when the number of inverters to be multiplexed is n, the switching frequency of each GTO is set to 1
It can be reduced to / n. Therefore, the allowable switching frequency of each element to be used may be 1 / n, so that the cost of the inverter device can be reduced.

Also, in the case of multiplexing, the DC current value to be cut off or cut off by each element may be 1 / n of that in the case of non-multiplexing, so the capacitance of capacitors 6 to 8 provided to absorb the overvoltage generated during switching. Can also be 1 / n.

Further, according to the embodiment of FIG. 1, as shown in FIG. 3, the operation is performed with 4π of the periods A and B as one cycle, so that the DC input voltage of the inverters INV1 and 2 is the average value of the periods A and B. Are equal, and the DC power supply can be shared. Although the instantaneous value of the DC input voltage is different, since it can be absorbed by the reactors 3 and 4 to this extent, the DC input currents of the inverters INV1 and INV2 can be balanced. Further, since the alternating voltage is applied to the reactors 3 and 4, the AC reactor can be used while the DC reactor 2 is used.

〔The invention's effect〕

As described above, according to the present invention, in parallel multiplexing of the inverters, it is possible to reduce the size by sharing the DC power supply unit of the main circuit,
Further, by adding a phase difference to the pulse pattern of each inverter, it is possible to obtain an effect that harmonics can be reduced.

In the above embodiment, the switching element is a GTO.
However, any element that has a reverse breakdown voltage can be used, and if an element that does not have a reverse breakdown voltage, such as a MOSFET or a bipolar transistor, is used, a composite element in which a series diode is connected to these elements is used at all. The same effect can be obtained.

Further, in the above embodiments, the multiplexing of two current source inverter devices using the self-extinguishing element is carried out, but the multiplexing of three or more inverter devices can be realized by the same method.

Further, it is obvious that the smoothing capacitor may be a delta connection instead of the Sitter connection.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a gate control circuit, FIG. 3 is a detailed view of essential parts of FIG. 2, and FIG. 4 is a pulse width modulation pattern signal. FIG. 5 is a waveform diagram of the gate signal, FIG. 6 is a waveform diagram of an operation explanatory diagram, FIG. 7 is a partially enlarged view of FIG. 6, and FIG. 8 is an operational explanatory diagram. A circuit diagram and FIG. 9 are waveform charts for explaining the effect of the present invention. 1,25 …… DC power supply, 3,4 …… AC reactor, 2 …… DC reactor, 5 …… Load, 6,7,8 …… Capacitor, 9
〜20 …… Self-extinguishing element, 21 …… Gate control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akiteru Ueda 4026 Kuji Town, Hitachi City, Ibaraki Prefecture, Hitate Manufacturing Co., Ltd.Hitachi Research Laboratories (72) Inventor Katsunori Suzuki 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Nitate Works In Hitachi Research Laboratory (72) Inventor Kazuhiko Sasaki 1070 Ige, Katsuta City, Ibaraki Hitachi Ltd. Mito Plant (56) References JP-A-56-86077 (JP, A) JP-A-59-132780 (JP, 132-780) A) JP-A-55-79684 (JP, A)

Claims (3)

[Claims] 1. At least two inverters each having a self-extinguishing element connected by Graet's connection are provided, and an AC output side of each inverter is connected in parallel to a load to be connected.
A main circuit section in which the same polarity on the DC input side of each of the inverters are connected by AC reactors, and DC power is supplied from the midpoint of each AC reactor via the DC reactor, and at least the output of the inverter A PWM pattern generation circuit that generates a pulse width modulation pattern signal that is predetermined for each cycle according to an output frequency command that commands a frequency, and a self-extinguishing element of the same phase arm of each inverter that receives the pulse width modulation pattern signal as an input A phase difference adding circuit for adding a phase difference to a pulse pattern control signal for controlling ON / OFF, and driving the self-extinguishing element of each inverter based on the control signal added with the phase difference between each inverter by the phase difference adding circuit And a control circuit section including a gate circuit for controlling the current source. 2. The phase difference adding circuit according to claim 1, wherein the pulse pattern in the 180-degree section of the in-phase arm of each inverter is the pulse pattern of one of the inverters of the other inverter. The multiple current source inverter device is characterized in that the start is delayed 30 degrees and the end is advanced 30 degrees with respect to the pulse pattern. 3. The method according to claim 2, wherein the addition of the lead or lag of the phase difference between the respective inverters is sequentially changed in each inverter at least every one cycle of the inverter output frequency. Multiplexed current source inverter device.