JPS6295649A - Memory back-up device - Google Patents

Abstract

PURPOSE:To protect the data on a memory means despite of the runaway of a CPU by latching the data on the memory means of a central processing unit with the signals produced in the CPU at the prescribed cycles. CONSTITUTION:A CPU 1 incorporates a RAM and produces signals in the prescribed cycles to reset a watchdog timer 2 and also to latch data to a latch circuit 3. When the CPU 1 runs away, no signal is outputted from the CPU 1 and the timer 2 counts up the time. Then a reset signal is outputted to the CPU 1 from the timer 2. Thus the CPU 1 is reset and at the same time the data latched by the circuit 3 are set to the RAM.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a memory bank up device that protects information stored in a memory in an electronic device using a central processing unit (hereinafter referred to as CPU) when the CPU goes out of control. Regarding.

[Prior art and its problems]

Conventionally, as shown in FIG. 3, for example, this type of device resets the watchdog timer 2 before the watchdog timer 2 counts up in response to a reset signal periodically output from the CPUI. There is a device in which the watchdog timer 2 performs count amplification and resets the CPLll because the cent signal is not output when the clock runs out of control.

However, with the watchdog timer described above, since the CPU only detects runaway and resets it, the Data cannot be protected. Therefore, for example, when a CPU is used in a copying machine, if the usage history data of the device, such as the number of sheets used and the usage time of the photosensitive drum, is stored in the RAM, the CPU
A problem occurs in which the data is lost due to the PU running out of control. Therefore, data such as the history of the device as described above is stored using a mechanical counter or the like.

In recent years, CMO8 single-chip CPUs with built-in RAM have become popular, and some of these CPUs have a protection function that protects data stored in the RAM when power is cut off.

However, even with this type of system, the data stored in RAM cannot be protected if the CPU goes out of control, and even if a watchdog timer is attached to it, the data stored in RAM cannot be protected.
There was a drawback that data stored in the RAM was lost due to a runaway of the PU.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above drawbacks, it is an object of the present invention to provide a memory backup device that can protect data stored in a memory even if the CPU goes out of control.

[Key points of the invention]

According to the present invention, the above object is achieved by the above-mentioned ↑, 9 means, a central processing unit that processes a predetermined sequence program and generates a signal at a predetermined period, and a central processing unit that processes the above-mentioned storage means every time the above-mentioned signal is generated. latching means for latching data; and setting means for detecting that the signal is not output from the central processing unit and setting the central processing unit to the initial state, and the setting means sets the central processing unit to the initial state. When set to , the data of the latch means is stored in the storage means.
This is achieved by providing a memory blow-up device which is characterized in that it restarts the operation of the central processing unit after the memory is blown up.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

In addition, the same parts as the conventional one are given the same reference numerals.

In FIG. 1, 1 is a CPtJ equipped with an internal RAM (not shown), and the usage history data such as the number of sheets used by the electrophotographic copying machine and the usage time of the photosensitive drum is stored in the RAM by the control operation of the CPU 1. It is supposed to be done. C.P.
The UI generates a signal at a predetermined cycle while processing a predetermined sequence program, and outputs the signal to a watchdog timer 2 and a latch circuit 3 for detecting runaway.

In normal operation, the watchdog timer 2 is reset for each periodic signal output from the CPU before the watchdog timer 2 performs count amplification, and at the same time, data in the RAM of the CPU is latched in the latch circuit 3 for each signal. In addition, when the CPU goes out of control, since no signal is output from the CPU 1 to the watchdog timer 2, the timer 2 performs count amplification, which outputs a reset signal from the watchdog timer 2 to reset the cput, and the CPU 1 Set to the initial state.

In this case, as shown in the flowchart of operation in FIG. 2, if the CPU returns to IM from runaway, the latch circuit 3
The latched data is set in the RAM again from the input port of the CPU t, and the operation is restarted. Note that at this time, the data latched in the latch circuit 3 is always equal to the RAM data before the CPU went out of control, so the CPU
Correct control operation continues by restarting the UI glue 3 creation. Reference numeral 4 denotes a backup power source when the power source (2) is cut off, and it is automatically switched to the bank-up power source 4 when the power source (2) is cut off by a diode OR circuit consisting of diodes DI and D2.

Note that in the above embodiment, the watchdog timer 2
The periodic signal output to the latch circuit 3 is
However, the present invention is not limited to this, and can be obtained by creating a timing signal with a predetermined period exclusively as a reset signal for the watchdog timer 2. In the case of a device equipped with this, it is also possible to use the signal generated to drive the display as the periodic signal.

With the above, when the CPU goes out of control,

Since the data is latched by the slave circuit 3 and stored in the RAM of the CPU, it is possible to prevent historical data such as the number of sheets used by the electrophotographic copying machine and the time period in which the photosensitive drums are used from being lost.

〔Effect of the invention〕

As explained above, according to the present invention, data is latched in the latch circuit when the CPU goes out of control, and the latched data is set in the storage means when the CPU returns to the normal state. This has the effect that stored data can be protected when the CPU goes out of control.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flow chart showing the operation of the present invention, and FIG. 3 is a schematic configuration diagram of a conventional device. ■...CPU. 2... Watch tong timer, 3... Latch circuit, 4... Hack-up power supply. Patent applicant: Casio Computer Co., Ltd. Above: Casio Electronics Co., Ltd. Figure 1

Claims (1)

[Scope of Claims] A storage means, a central processing unit that processes a predetermined sequence program and generates a signal at a predetermined cycle, and a latch means that latches data in the storage means each time the signal is generated. and a setting means for detecting that the signal is not output from the central processing unit and setting the central processing unit to an initial state, and when the central processing unit is set to the initial state by the setting means, A memory backup device characterized in that the operation of the central processing unit is restarted after the data of the latch means is set in the storage means.