WO2020119532A1

WO2020119532A1 - Processor control method and apparatus, and storage medium

Info

Publication number: WO2020119532A1
Application number: PCT/CN2019/122785
Authority: WO
Inventors: 侯方西
Original assignee: 中兴通讯股份有限公司
Priority date: 2018-12-13
Filing date: 2019-12-03
Publication date: 2020-06-18
Also published as: CN111324494A; CN111324494B

Abstract

A processor control method and apparatus, a computer device, and a storage medium. The method comprises: determining whether level conversion occurs in an output signal of a timing circuit (S201); if level conversion occurs in the output signal of the timing circuit, detecting an interactive interface corresponding to a first processor is abnormal (S202); if the interactive interface corresponding to the first processor is abnormal, generating a restart signal (S203); and sending the restart signal to the first processor so as to restart the first processor (S204). A second processor actively monitors the operating state of the first processor by means of the timing circuit, if detecting that the first processor is abnormal, detects whether the interactive interface corresponding to the first processor is abnormal, and if the interactive interface is abnormal, generates a restart signal, and sends the restart signal to the first processor so as to restart the first processor.

Description

Processor control method, device and storage medium

This disclosure claims the priority of the Chinese patent application CN201811526932.4, entitled "Processor Control Method, Device, and Storage Media," filed on December 13, 2018, the entire contents of which are incorporated herein by reference.

Technical field

The present disclosure relates to the field of communication technologies, and in particular, to a processor control method, device, computer equipment, and storage medium.

Background technique

On the 5G platform, the current common interaction interfaces between multiple processors include: PCIe, USB, UART and GPIO interfaces, similar to the previous dual-mode machine architecture, but when one of the processor software exceptions may cause all GPIO, UART and other levels are locked, and these interfaces may maintain high or low levels. The high and low levels maintained here are random, but no matter which level is maintained, these interfaces are The effective information cannot be transmitted, so the interactive interface loses its function and cannot actively notify the main processor, and the main processor cannot learn the state of the first processor.

Summary of the invention

In order to solve the above technical problem, the present disclosure provides an exception handling method of the first processor.

A processor control method, a multiprocessor includes a main processing and a first processor, including:

A processor control method is applied to a processor system including at least a first processor and a second processor. The first processor sends a reset signal to a timing circuit at a first time interval in the working state. The method includes: judging Whether the output signal of the timing circuit is level shifted; when the output signal of the timing circuit is level shifted, it is detected whether the interactive interface corresponding to the first processor is abnormal; when the interactive interface corresponding to the first processor is abnormal, it is generated Restart signal; send a restart signal to the first processor to restart the first processor.

A processor control device is applied to a processor system including at least a first processor and a second processor. The device includes: a sending module, and the first processor sends a reset signal to the timer at a first time interval in the working state Circuit; timing circuit signal detection module, used to determine whether the output signal of the timing circuit has a level shift; interface abnormality detection module, used to detect the interaction corresponding to the first processor when the output signal of the timing circuit has a level shift Whether the interface is abnormal; the signal generation module is used to generate a restart signal when the interactive interface corresponding to the first processor is abnormal; the restart module is used to send the restart signal to the first processor so that the first A processor restarts.

A computer device, comprising: a first processor, a second processor and a memory, the memory stores a computer program, and when the computer program is executed by the second processor, the second processor Perform the following steps: determine whether the output signal of the timing circuit has a level shift; when the output signal of the timing circuit has a level shift, detect whether the interaction interface corresponding to the first processor is abnormal; when the interaction corresponds to the first processor When the interface is abnormal, a restart signal is generated; a restart signal is sent to the first processor to restart the first processor.

A computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the following steps are realized: judging whether the output signal of the timing circuit has a level shift; when the output signal of the timing circuit has a level shift At the time, detect whether the interactive interface corresponding to the first processor is abnormal; when the interactive interface corresponding to the first processor is abnormal, generate a restart signal; send a restart signal to the first processor to restart the first processor.

BRIEF DESCRIPTION

The drawings herein are incorporated into and constitute a part of this specification, show embodiments consistent with this disclosure, and are used together with the specification to explain the principles of this disclosure.

In order to more clearly explain the technical solutions in the embodiments or some cases of the present disclosure, the following will briefly introduce the drawings that need to be used in the embodiments or some cases. Obviously, for those of ordinary skill in the art, in On the premise of not paying creative labor, other drawings can also be obtained from these drawings.

FIG. 1 is an application scenario diagram of a processor control method in an embodiment;

2 is a schematic flowchart of a processor control method in an embodiment;

3 is an application scenario diagram of a processor control method in an embodiment;

4 is a structural block diagram of a processor control device in an embodiment;

5 is a block diagram of the internal structure of a computer device in an embodiment.

detailed description

To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments It is a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

FIG. 1 is an application environment diagram of a processor control method in an embodiment. Referring to FIG. 1, the processor control method is applied to a terminal. The terminal includes at least a first processor 110 and a second processor 120. The first processor 110 and the second processor 120 are connected through an interface. In the working state, the first processor 110 sends a reset signal to the timing circuit at a first time interval, and the second processor 120 determines whether the output signal of the timing circuit has a level Conversion, when the output signal of the timing circuit is level-shifted, it is detected whether the interactive interface corresponding to the first processor 110 is abnormal, and when the interactive interface corresponding to the first processor 110 is abnormal, a restart signal is generated to the first processing The processor 110 sends a restart signal to restart the first processor. The first processor 110 and the second processor 120 are common processors. The first processor 110 and the second processor 120 are only used to distinguish different processors.

As shown in FIG. 2, in one embodiment, a processor control method is provided. This embodiment is mainly exemplified by the method applied to the second processor 120 in FIG. 1 described above. Referring to FIG. 2, the processor control method includes the following steps:

In step S201, it is determined whether the output signal of the timing circuit has a level shift.

Step S202, when the output signal of the timing circuit undergoes a level shift, it is detected whether the interactive interface corresponding to the first processor is abnormal.

In one embodiment, the timing circuit is a circuit for timing, including a watchdog timeout circuit. The reset signal refers to a prompt signal sent by the first processor to indicate the normal operation of the first processor, wherein the reset signal sent by the first processor is used to restart the timing circuit, and the maximum time interval for sending the reset signal is the first duration , By sending a reset signal to ensure that the level signal output by the timing circuit has not been converted. The working state of the first processor includes normal and abnormal states. The abnormality of the first processor refers to the crash of the first processor. The causes of the crash of the first processor include, but are not limited to, software main program crashes and hardware abnormalities. Crash. When the output signal of the timing circuit changes level, it indicates that the first processor is in an abnormal state, and the interactive interface corresponding to the first processor is detected. The interactive interface refers to the interface between the first processor and the second processor. Including but not limited to PCIe, USB, UART, GPIO, etc.

In one embodiment, the first duration is greater than the sleep period of the first processor. The first processor has a sleep-wake-sleep cycle. Since the sleep time of the general first processor is greater than the sleep time of the main processor, the first time can be avoided when the first duration is set to be longer than the sleep duration of the first processor There is no abnormality in the processor, only the error message brought during the sleep cycle.

In one embodiment, a watchdog timeout circuit is provided between the first processing and the second processor, where the watchdog timeout circuit is a component of the single-chip microcomputer and is a counter, and the first processor times out the watchdog A number in the circuit, the watchdog timeout circuit starts to count down after the program starts running. If the program runs normally, after a while, the first processor should issue an instruction to reset the watchdog timeout circuit and restart the countdown. If the watchdog timeout circuit is reduced to 0, the level signal output by the timeout circuit is converted, it is considered that the first processor is not working normally, and it is judged that the first processor is abnormal.

In one embodiment, detecting whether the interactive interface corresponding to the first processor is abnormal includes sending a level conversion signal to the interactive interface corresponding to the first processor to detect the level of the interactive interface corresponding to the first processor Whether to convert, when not converted, it is determined that the interactive interface corresponding to the first processor is abnormal.

In one embodiment, the level conversion signal refers to a level signal obtained by performing conversion processing on the level signal, such as a level-up or level-down signal. After detecting the abnormality of the first processor, it sends a level conversion signal to the interactive interface corresponding to the first processor, such as lowering the level of GPIO, sending a corresponding interrupt signal, responding to the interrupt signal, and obtaining the power of the GPIO by responding to the interrupt signal If the level sent by the first processor to the GPIO has changed, it means that the level sent by the first processor to the GPIO has not changed, indicating that the interactive interface is abnormal. Among them, the interrupt signal refers to a signal that has been previously defined to indicate interruption.

Step S203, when the interactive interface corresponding to the first processor is abnormal, a restart signal is generated.

Step S204: Send a restart signal to the first processor to restart the first processor.

In one embodiment, the restart signal refers to a computer instruction or level signal used to instruct the processor to restart. The abnormality of the interactive interface corresponding to the first processor means that the interactive interface corresponding to the first processor cannot perform data interaction normally. In order to restore the normal data interaction of the interactive interface, it is necessary to restart the first process to achieve it, so after detecting the interactive interface A restart signal is produced, a restart signal is sent to the first process, and the first processor is restarted by the restart signal.

In one embodiment, the restart signal is a power start level signal, and a power start level signal corresponding to the first processor is generated. The power supply start level signal refers to a level signal used to start the power supply.

In one embodiment, the field data of the process associated with the first processor is acquired, and the interval associated with the first processor is resumed based on the field data after the restart signal is sent to the first processor for a second time interval.

In one embodiment, the process associated with the first processor refers to the process that the first processor is executing when it is working normally. On-site data refers to the data being processed by various processes and data processing rules. The second duration is a preset time threshold. The time threshold can be customized. For example, it can be set according to the type of the first processor. Different types of chips have different restart times. Therefore, the corresponding interval can be adjusted according to the chip. Obtain the field data of the first processor related process, after sending a restart signal to the first processor, when the interval is the second duration, in the recovery of the related process, choose to start the recovery of the relevant process after the second interval, because the second The duration includes the startup time of the first processor. If the level of the GPIO is at a high level before the abnormality occurs, the level of the GPIO will be restored to a high level, and the conversion rule of the GPIO circuit, if the level of the UART is at a low level, the UART will be restored The status of the level is low, and the level conversion law of the UART is restored.

The above processor control method is applied to a processor system including at least a first processor and a second processor. In the working state, the first processor sends a reset signal to the timing circuit at a first time interval to determine whether the output signal of the timing circuit Level conversion occurs, when the output signal of the timing circuit changes level, it is detected whether the interactive interface corresponding to the first processor is abnormal, and when the interactive interface corresponding to the first processor is abnormal, a restart signal is generated to the first The processor sends a restart signal to restart the first processor. The second processor actively monitors the working state of the first processor through a timing circuit. When an abnormality of the first processor is detected, the working state of the interactive interface corresponding to the first processor is detected. When the interactive interface is abnormal , Then actively generate a restart signal to restart the first processor. With this processing monitoring method, the abnormality of the first processor can be sensed by the second processor in time, the intervention of the second processor on the first processor is introduced, and the working state of the first processor is restored by the active operation of the second processor, Therefore, real-time monitoring and abnormal real-time recovery of the first processor are realized, so that the processor system is more stable and reliable.

In some cases, the first processor cannot actively inform the second processor. The second processor uses the interactive interface with the first processor to query the status of the first processor, and then determines the abnormal condition of the first processor, and Polling is generally used for inquiries. Since the second processor only actively interacts with the first processor when it is initiated by the user and requires the participation of the first processor, it cannot guarantee real-time perception of the working state of the first processor. The data and voice services that a processor is responsible for cannot be transmitted to the second processor, resulting in the processor system not functioning normally.

In one embodiment, the above processor control method, as shown in FIG. 3, the system is a dual-processor system, including a master processor and a slave processor, the master processor is a second processor, and the slave processor is a first processing A watchdog timeout circuit is provided between the master processor and the slave processor. The slave processor feeds the dog, and the watchdog timeout circuit feeds back to the master processor. The interfaces between the master processor and the slave processor include but are not limited to PCIe, USB, UART, GPIO and other interfaces.

The terminal contains a multi-processor system. When the slave processor crashes, the level of the interface between the master processor and the slave processor is locked, such as the level of the GPIO, UART and other interfaces. The level of each interface may be at The high-level state may also be in a low-level state. The specific state is related to the work performed by each interface. After the level is locked, valid information cannot be transmitted. After the level is locked, the slave processor cannot send the dog feed signal. After the watchdog timeout circuit times out, it sends an abnormal terminal signal to the main process. When the master processor receives the abnormal interrupt signal, it immediately queries whether the normal interactive interface is There is feedback, such as pulling down the GPIO to send an interrupt signal, querying whether the level of the corresponding GPIO sent from the slave processor to the master processor changes, if the interface has no level change, then keep the scene and restart the slave processor circuit.

Since the multi-processor system of the mobile terminal has a sleep-wake-sleep cycle, the slave processor sleeps before the master processor and wakes up later than the master processor. The slave processor is in the wakeup state FEED (feeding the dog), set the watchdog delay time to be greater than the sleep cycle of the slave processor, when the slave processor wakes up, the normal working state can feed the dog, if the slave software crashes, it cannot feed Dogs, such as pulse signals and two level logic transitions, the watchdog timeout circuit times out, and the bark signal is output to notify the main processor to perform exception handling, regardless of whether it is in a sleep state or awake state, the main processor supplies power from the slave processor The power switch signal restarts the slave processor.

In the above processor control method, the feed program of the first processor is used to feed the dog to the watchdog timeout circuit. When an abnormality occurs in the first processor, the feed program of the first processor is not to feed the dog to the watchdog timeout circuit ( Feed_In), causing the watchdog timeout circuit to time out, sending a feedback signal (Bark_Out) to the second processor that the first processor has an abnormality, sending the query request through the second processor, and determining the first processing according to the query result of the query request Whether there is an abnormality in the device, if it is determined that an abnormality occurs, restart the first processor through POWER_ON, you can understand the working state of the first processor in real time, and handle the abnormal state of the first processor in time to ensure the normal operation of the mobile terminal .

FIG. 2 is a schematic flowchart of a processor control method in an embodiment. It should be understood that although the steps in the flowchart of FIG. 2 are displayed in order according to the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless clearly stated in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in FIG. 2 may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed and completed at the same moment, but may be executed at different moments, the execution of these sub-steps or stages The order is not necessarily sequential, but may be executed in turn or alternately with at least a part of other steps or sub-steps or stages of other steps.

In one embodiment, as shown in FIG. 4, a processor control device 200 is provided, which is applied to a processor system including at least a first processor and a second processor. The device includes: a sending module 201, a A processor sends a reset signal to the timing circuit at the first time interval in the working state. The timing circuit signal detection module 202 is used to determine whether the output signal of the timing circuit has a level shift. The interface abnormality detection module 203 is configured to detect whether the interactive interface corresponding to the first processor is abnormal when the output signal of the timing circuit changes level. The signal generation module 204 is configured to generate a restart signal when the interactive interface corresponding to the first processor is abnormal. The restart module 205 is configured to send the restart signal to the first processor to restart the first processor.

In one embodiment, the processor control device 200 described above further includes: a data acquisition module, configured to acquire field data of a process associated with the first processor. The process recovery module is configured to recover the process associated with the first processor according to the on-site data after a second time interval after sending the restart signal to the first processor.

In one embodiment, the interface abnormality detection module 203 includes: a level signal sending unit, configured to send a level conversion signal to an interactive interface corresponding to the first processor. The level detection unit is used to detect whether the level of the interactive interface corresponding to the first processor is switched. The interface abnormality determining unit is used to determine that the interactive interface corresponding to the first processor is abnormal when it is not converted.

In one embodiment, the first duration in the processor abnormality determination module 303 is greater than the sleep time of the first processor.

In one embodiment, the signal generation module 204 is also used to generate a power-on level signal corresponding to the first processor.

FIG. 5 shows an internal structure diagram of a computer device in an embodiment. The computer device may be the second processor 120 in FIG. 1. As shown in FIG. 5, the computer device includes the computer device including a first processor, a second processor, a memory, a network interface, an input device, and a display screen connected through a system bus. Among them, the memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program. When the computer program is executed by the processor, the processor may cause the processor to implement the processor control method. A computer program may also be stored in the internal memory. When the computer program is executed by the second processor, the second processor may cause the second processor to execute the processor control method. The display screen of the computer device may be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device may be a touch layer covered on the display screen, or may be a button, a trackball or a touch pad provided on the casing of the computer device. It can be an external keyboard, touchpad or mouse.

Those skilled in the art can understand that the structure shown in FIG. 5 is only a block diagram of a part of the structure related to the disclosed solution, and does not constitute a limitation on the computer device to which the disclosed solution is applied. The computer device may include a ratio More or fewer components are shown in the figure, or some components are combined, or have different component arrangements.

In one embodiment, the processor control apparatus provided by the present disclosure may be implemented in the form of a computer program, and the computer program may run on the computer device shown in FIG. 5. The memory of the computer device may store various program modules constituting the processor control device, for example, the timing module 201, the judgment module 202, the signal receiving module 203, the query module 204, and the restart module 205 shown in FIG. The computer program constituted by each program module causes the processor to execute the steps in the processor control method of each embodiment of the present disclosure described in this specification.

For example, the computer device shown in FIG. 5 may execute the sending module 201 in the processor control apparatus shown in FIG. 4 to execute the first processor to send a reset signal to the timing circuit at a first time interval in the working state. The computer device may be executed by the timing circuit signal detection module 202 and used to determine whether the output signal of the timing circuit has undergone a level shift. The computer device may perform, through the interface abnormality detection module 203, when the output signal of the timing circuit undergoes level conversion, detecting whether the interactive interface corresponding to the first processor is abnormal. The computer device may execute the signal generation module 204 to generate a restart signal when the interactive interface corresponding to the first processor is abnormal. The computer device may execute a restart signal sent to the first processor through the restart module 205 to restart the first processor.

In one embodiment, a computer device is provided, including a memory, a first process and a second processor, and a computer program stored on the memory and executable on the second processor, when the second processor executes the computer program The following steps are implemented: judging whether the output signal of the timing circuit has a level shift, when the output signal of the timing circuit has a level shift, detecting whether the interaction interface corresponding to the first processor is abnormal, and when the interaction corresponding to the first processor When the interface is abnormal, a restart signal is generated, and a restart signal is sent to the first processor to restart the first processor.

In one embodiment, the processor also implements the following steps when executing the computer program: acquiring field data of a process associated with the first processor, and sending a restart signal to the first processor at a second time interval, and recovering from The process associated with the first processor.

In one embodiment, the first duration is greater than the sleep time of the first processor.

In one embodiment, generating the restart signal includes generating a power start level signal corresponding to the first processor.

In one embodiment, a computer-readable storage medium is provided on which a computer program is stored. When the computer program is executed by a processor, the following steps are realized: whether the output signal of the timing circuit is level-shifted, when the timing circuit When the output signal is level-shifted, it is detected whether the interactive interface corresponding to the first processor is abnormal. When the interactive interface corresponding to the first processor is abnormal, a restart signal is generated and the restart signal is sent to the first processor, so that the first A processor restarts.

Those of ordinary skill in the art may understand that all or some of the steps, systems, and functional modules/units in the method disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical The components are executed in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit . Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes both volatile and nonvolatile implemented in any method or technology for storing information such as computer readable instructions, data structures, program modules, or other data Sexual, removable and non-removable media. Computer storage media include but are not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium for storing desired information and accessible by a computer. In addition, it is well known to those of ordinary skill in the art that the communication medium generally contains computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium .

The above-mentioned processor control method, device, computer equipment and storage medium, the method is based on judging whether the output signal of the timing circuit has a level shift, and when the output signal of the timing circuit has a level shift, detecting corresponding to the first processor Whether the interactive interface of the server is abnormal, when the interactive interface corresponding to the first processor is abnormal, a restart signal is generated, and a restart signal is sent to the first processor to restart the first processor. The second process actively monitors the working state of the first processor through a timing circuit. When an abnormality of the first processor is detected, it is detected whether the interactive interface corresponding to the first processor is abnormal, and when the interactive interface is abnormal, a restart signal is generated, A restart signal is sent to the first processor to restart the first processor, and the second processor actively queries the working state of the first processor in real time, so that the problems occurring in the first processor can be resolved in time.

It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these There is any such actual relationship or order between entities or operations. Moreover, the terms "include", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also those not explicitly listed Or other elements that are inherent to this process, method, article, or equipment. Without more restrictions, the element defined by the sentence "include one..." does not exclude that there are other identical elements in the process, method, article or equipment that includes the element.

The above are only specific implementations of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features applied herein.

Claims

A processor control method is applied to a processor system including at least a first processor and a second processor. The first processor sends a reset signal to a timing circuit at a first time interval in the working state. The method includes :

Judging whether the output signal of the timing circuit has a level shift;

When the output signal of the timing circuit undergoes a level shift, it is detected whether the interactive interface corresponding to the first processor is abnormal;

When the interactive interface corresponding to the first processor is abnormal, a restart signal is generated;

Sending the restart signal to the first processor to restart the first processor.
The method of claim 1, wherein the method further comprises:

Acquiring on-site data of processes associated with the first processor;

After sending the restart signal to the first processor for a second time interval, the process associated with the first processor is resumed according to the on-site data.
The method according to claim 1, wherein the detecting whether the interactive interface corresponding to the first processor is abnormal includes:

Sending a level conversion signal to the interactive interface corresponding to the first processor;

Detecting whether the level of the interactive interface corresponding to the first processor is switched;

When not converted, it is determined that the interactive interface corresponding to the first processor is abnormal.
The method of claim 1, wherein the first duration is greater than the sleep time of the first processor.
The method according to any one of claims 1 to 4, wherein the generating a restart signal includes:

Generating a power-on level signal corresponding to the first processor.
A processor control device is applied to a processor system including at least a first processor and a second processor, wherein the device includes:

A sending module, used for a processor system including at least a first processor and a second processor, the first processor sends a reset signal to the timing circuit at a first time interval in the working state;

The timing circuit signal detection module is used to determine whether the output signal of the timing circuit has a level shift;

An interface abnormality detection module, configured to detect whether the interactive interface corresponding to the first processor is abnormal when the output signal of the timing circuit changes level;

A signal generating module, configured to generate a restart signal when the interactive interface corresponding to the first processor is abnormal;

The restart module is configured to send the restart signal to the first processor to restart the first processor.
The device according to claim 6, wherein the device further comprises:

A data acquisition module, used to acquire field data of the process associated with the first processor;

The process recovery module is configured to recover the process associated with the first processor according to the on-site data after a second time interval after sending the restart signal to the first processor.
The apparatus according to claim 6, wherein the interface abnormality detection module further comprises:

A level signal sending unit, configured to send a level conversion signal to the interactive interface corresponding to the first processor;

A level detection unit, configured to detect whether the level of the interactive interface corresponding to the first processor is switched;

The interface abnormality determining unit is configured to determine that the interactive interface corresponding to the first processor is abnormal when not converted.
A computer device, comprising: a first processor, a second processor and a memory, the memory stores a computer program, and when the computer program is executed by the second processor, the second processor The steps of the method according to any one of claims 1 to 5 are performed.
A computer-readable storage medium having stored thereon a computer program, wherein when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are realized.