CN205620932U - Resetting means of multiple microprocessors system and monitor thereof - Google Patents
Resetting means of multiple microprocessors system and monitor thereof Download PDFInfo
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- CN205620932U CN205620932U CN201620228178.6U CN201620228178U CN205620932U CN 205620932 U CN205620932 U CN 205620932U CN 201620228178 U CN201620228178 U CN 201620228178U CN 205620932 U CN205620932 U CN 205620932U
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Abstract
The utility model provides a resetting means of multiple microprocessors system and monitor thereof, the resetting means of multiple microprocessors system includes mutual communication connection's a microprocessor and the 2nd microprocessor at least, a microprocessor includes a host system and the first module that restores to the throne, first reset the module with a host system is connected, the 2nd microprocessor includes the 2nd host system and the second module that restores to the throne, the second reset the module with host system is connected, first reset module and second reset the module and are connected. Microprocessor among a microprocessor and the 2nd microprocessor regards as the foundation of judging of whether normal operating with another microprocessor's indicator signal, make full use of the existing resource, simplified the circuit, saved the cost.
Description
Technical field
This utility model relates to medical monitoring field, particularly relates to a kind of multi-micro processor system resetting means, and relates to the monitor including this multi-micro processor system resetting means.
Background technology
In monitor hardware board, according to system requirements, multi-microprocessor system is there may be on one board, as included 2 or more than 2 microprocessor systems, in order to ensure system reliability service, prevent microprocessor internal program from entering endless loop, each microprocessor can design corresponding reset circuit, when microprocessor internal program occurs abnormal, microprocessor is resetted by reset circuit, thus ensures system roll-back.
Fig. 2 is existing scheme hardware block diagram, illustrate as a example by two-processor system, existing scheme typically can be individually to each microprocessor Design watchdog circuit, it does not interfere with each other between each watchdog circuit, when microprocessor internal program occurs abnormal, microprocessor can be resetted by watchdog circuit, makes microprocessor rerun.
The fundamental diagram of watchdog circuit is, microprocessor sends feeding-dog signal according to the time of regulation to watchdog circuit by I/O port, if microprocessor internal program is normal, then feeding-dog signal is normal, watchdog circuit can the most constantly receive feeding-dog signal, then watchdog circuit will not send reset signal to microprocessor.If microprocessor internal program exception, the feeding-dog signal that then microprocessor sends is abnormal, if watchdog circuit does not receives feeding-dog signal within the time of regulation, then watchdog circuit can send reset signal to microprocessor, make microprocessor reset, after reset completes, microprocessor internal program is the most properly functioning.Existing scheme have employed the watchdog circuit of multichannel independence, and circuit is more complicated, underuses existing system resource, relatively costly.
Summary of the invention
Technical problem to be solved in the utility model is to need to provide one to simplify circuit, the multi-micro processor system resetting means provided cost savings, and provides the monitor including this multi-micro processor system resetting means.
To this, this utility model provides a kind of multi-micro processor system resetting means, at least include first microprocessor and the second microprocessor being in communication with each other connection, described first microprocessor includes that the first main control module and the first reseting module, described first reseting module are connected with described first main control module；Described second microprocessor includes that the second main control module and the second reseting module, described second reseting module are connected with described main control module；One reseting module of described first reseting module and the second reseting module at least includes the transmission reseting module for sending reset signal, and another reseting module at least includes the reception reseting module for receiving reset signal.
Further, described multi-micro processor system resetting means includes at least two microprocessor, and between two adjacent microprocessors, cascade connects.
Further, described first microprocessor also includes that first timer module, described first timer module are connected with described first main control module.
Further, described second microprocessor also includes that second timer module, described second timer module are connected with described second main control module.
Further, described first reseting module includes that the first reception reseting module and first being connected with described first main control module respectively sends reseting module, described second reseting module includes that the second reception reseting module and second being connected with described second main control module respectively sends reseting module, and described first receives reseting module is connected with described second transmission reseting module；Described first sends reseting module is connected with described second reception reseting module.
Further, described first microprocessor also includes feeding Canis familiaris L. module, the watchdog module that described first main control module is externally connected by feeding Canis familiaris L. module.
Further, also including isolation module, described first microprocessor is connected to described second microprocessor by isolation module.
Further, described first reseting module includes the first transmission reseting module, described isolation module includes isolating circuit module, and described second reseting module includes the second reception reseting module, and described first sends reseting module is connected to described second reception reseting module by isolation circuit module.
Further, described first microprocessor also includes first communication module, described second microprocessor also includes second communication module, and described isolation module also includes isolating communication module, and described first communication module is connected to described second communication module by isolation communication module.
Further, described first microprocessor also includes that first timer module, described first timer module are connected with described first main control module；Described first reseting module also includes the first reception reseting module, and described watchdog module receives reseting module by described first and is connected to described first main control module.
This utility model also provides for a kind of monitor, and described monitor includes multi-micro processor system resetting means as above.
nullCompared with prior art，The beneficial effects of the utility model are: realize the transmission of reset signal between described first reseting module and the second reseting module，Described first communication module is connected with second communication module and realizes the transmission of communication data，Make a microprocessor in first microprocessor and the second microprocessor using the indication signal of another microprocessor as the most properly functioning judgment basis of system，This indication signal can be the signal of communication between first microprocessor and the second microprocessor，Can also be that certain signal specific of sending to another microprocessor of a microprocessor etc. is any can reflect the signal of association between two microprocessors，This signal specific can be square wave、Sine wave or clock signal etc.，If a microprocessor in first microprocessor and the second microprocessor does not receives the normal indication signal of another microprocessor，This microprocessor sends reset signal to another microprocessor，Another microprocessor system is resetted；The technical solution of the utility model owing to taking full advantage of existing resource, Rational Simplification circuit, provide cost savings.
Accompanying drawing explanation
Fig. 1 is the circuit block diagram of the multi-micro processor system resetting means of a kind of embodiment of this utility model；
Fig. 2 is multimicroprocessor reset circuit block diagram of the prior art；
Fig. 3 is the circuit block diagram of the multi-micro processor system resetting means of this utility model another kind embodiment；
Fig. 4 is the circuit block diagram of the multi-micro processor system resetting means of this utility model another embodiment.
Detailed description of the invention
Below in conjunction with the accompanying drawings, preferably embodiment of the present utility model is described in further detail.
Embodiment 1:
As shown in Figure 1, the present embodiment provides a kind of multi-micro processor system resetting means, at least include first microprocessor 10 and the second microprocessor 20, described first microprocessor 10 includes the first main control module the 11, first reseting module and first communication module 13, and described first reseting module is connected with described first main control module 11 respectively with first communication module 13；Described second microprocessor 20 includes the second main control module the 21, second reseting module and second communication module 23, and described second reseting module is connected with described main control module respectively with second communication module 23；A reseting module in described first reseting module and the second reseting module at least includes the transmission reseting module for sending reset signal, another reseting module at least includes the reception reseting module for receiving reset signal, and described first communication module 13 is connected with second communication module 23.
First reseting module described in the present embodiment and the second reseting module are connected, in described first reseting module and the second reseting module the two reseting module, one reseting module at least includes the transmission reseting module for sending reset signal, and another reseting module at least includes the reception reseting module for receiving reset signal；That is, a microprocessor in adjacent two microprocessors at least includes the transmission reseting module for sending reset signal, and another microprocessor at least includes the reception reseting module for receiving reset signal.Described in the present embodiment, multi-micro processor system resetting means includes at least two microprocessor, between two adjacent microprocessors, cascade connects, that is, this example is not limited to two microprocessors, as long as being capable of the transmission of reset signal between adjacent two microprocessors.
Such as, when described multi-micro processor system resetting means includes two microprocessors, if the first reseting module of first microprocessor 10 is the transmission reseting module for sending reset signal, then the second reseting module of the second microprocessor 20 is the reception reseting module for receiving reset signal；Vice versa.The most such as, when described multi-micro processor system resetting means includes the microprocessor that three cascade successively, if the first reseting module of first microprocessor 10 is the transmission reseting module for sending reset signal, then the second reseting module of the second microprocessor 20 is the reception reseting module for receiving reset signal, as a same reason, 3rd microprocessor is also equipped with realizing the module that reset signal is transmitted, by that analogy with the second microprocessor 30.
In the present embodiment, described first reseting module and the second reseting module are connected the transmission for realizing reset signal；Described first microprocessor 10 also includes that first timer module 15, described first timer module 15 are connected with described first main control module 11；Described second microprocessor 20 also includes that second timer module 25, described second timer module 25 are connected with described second main control module 21；Described first reseting module includes that the first reception reseting module 16 and first being connected with described first main control module 11 respectively sends reseting module 14, described second reseting module includes that the second reception reseting module 26 and second being connected with described second main control module 21 respectively sends reseting module 24, and described first receives reseting module 16 is connected with described second transmission reseting module 24；Described first sends reseting module 14 is connected with described second reception reseting module 26.
Described first microprocessor 10 is communicated with described second microprocessor 20 by first communication module 13, if first micro-process 10 has been received by the communication data of the second microprocessor 20 at the appointed time, then first micro-process 10 is not to 20 reset signals of the second microprocessor, and the second microprocessor 20 continues normally to work；If first micro-process 10 does not receives the communication data of the second microprocessor 20 at the appointed time, then first microprocessor 10 sends reset signal to the second microprocessor 20, makes the second microprocessor 20 reset.
In the present embodiment, described first main control module 11 is used for controlling first communication module the 13, first transmission reseting module 14, first timer module 15 and first receives the co-ordination between reseting module 16.First communication module 13 is connected with the first main control module 11 and second communication module 23 respectively, it is achieved the communication function between first microprocessor 10 and the second microprocessor 20.Described first sends reseting module 14 is connected, for sending reset signal to the second microprocessor 20 with described first main control module 11 and the second reception reseting module 26 respectively；When first microprocessor 10 has been received by the communication data of the second microprocessor 20 at the appointed time, then the first transmission reseting module 14 is not to 20 reset signals of the second microprocessor, and the second microprocessor 20 continues normally to work；If first microprocessor 10 does not receives the communication data of the second microprocessor 20 at the appointed time, then the first transmission reseting module 14 sends reset signal to the second microprocessor 20, makes the second microprocessor 20 reset.Described first timer module 15 is connected with described first main control module 11, it is achieved timing function, so that it is determined that first microprocessor 10 receives the signal of communication of the second microprocessor 20 the most at the appointed time.Described first receives reseting module 16 is connected, for receiving the reset signal that the second microprocessor 20 sends with the first main control module 11 and the second transmission reseting module 24 respectively.
Described second microprocessor 20 is connected with described first microprocessor 10, communicated with described first microprocessor 10 by second communication module 23, if the second microprocessor 20 has been received by the communication data of first microprocessor 10 at the appointed time, then the second microprocessor 20 is not to 10 reset signals of first microprocessor, and first microprocessor 10 continues normally to work；If the second microprocessor 20 does not receives the communication data of first microprocessor 10 at the appointed time, then the second microprocessor 20 sends reset signal to first microprocessor 10, makes first microprocessor 10 reset.Second main control module 21 is used for controlling second communication module the 23, second transmission reseting module 24, second timer module 25 and second receives the co-ordination between reseting module 26.Described second communication module 23 is connected with the second main control module 21 and first communication module 13 respectively, it is achieved the communication function between the second microprocessor 20 and first microprocessor 10.Described second sends reseting module 24 is connected with the second main control module 21 and the first reception reseting module 16 respectively, for sending reset signal to first microprocessor 10, when the second microprocessor 20 has been received by the communication data of first microprocessor 10 at the appointed time, then the second transmission reseting module 24 is not to 10 reset signals of first microprocessor, and first microprocessor 10 continues normally to work；If the second microprocessor 20 does not receives the communication data of first microprocessor 10 at the appointed time, then the second transmission reseting module 24 sends reset signal to first microprocessor 10, makes first microprocessor 10 reset.Described second timer module 25 is connected with the second main control module 21, it is achieved timing function, so that it is determined that the second microprocessor 20 receives the signal of communication of first microprocessor 10 the most at the appointed time.Described second receives reseting module 26 is connected, for receiving the reset signal that first microprocessor 10 sends with second main control module the 21, first transmission reseting module 14 respectively.
nullThe transmission of reset signal is realized between first reseting module and the second reseting module described in the present embodiment，Described first communication module 13 is connected with second communication module 23 and realizes the transmission of communication data，Make a microprocessor in first microprocessor 10 and the second microprocessor 20 using the indication signal of another microprocessor as the most properly functioning judgment basis of system，This indication signal can be the signal of communication between first microprocessor 10 and the second microprocessor 20，Can also be that certain signal specific of sending to another microprocessor of a microprocessor etc. is any can reflect the signal of association between two microprocessors，This signal specific can be square wave、Sine wave or clock signal etc.，If a microprocessor in first microprocessor 10 and the second microprocessor 20 does not receives the normal indication signal of another microprocessor，This microprocessor sends reset signal to another microprocessor，Another microprocessor system is resetted；The technical scheme of the present embodiment owing to taking full advantage of existing resource, Rational Simplification circuit, provide cost savings.
Embodiment 2:
As shown in Figure 3, the present embodiment provides a kind of multi-micro processor system resetting means, at least include first microprocessor 10 and the second microprocessor 20, described first microprocessor 10 includes that first main control module the 11, first reseting module, first communication module 13 and first timer module 15, described first reseting module, first communication module 13 and first timer module 15 are connected with described first main control module 11 respectively；Described second microprocessor 20 includes the second main control module the 21, second reseting module and second communication module 23, and described second reseting module is connected with described main control module respectively with second communication module 23；Realizing the transmission of reset signal between described first reseting module and the second reseting module, described first communication module 13 is connected with second communication module 23.
As different from Example 1, as it is shown on figure 3, first microprocessor 10 described in the present embodiment also includes feeding Canis familiaris L. module 12, the watchdog module that described first main control module 11 is externally connected by feeding Canis familiaris L. module 12；Described multi-micro processor system resetting means also includes isolation module, and described first microprocessor 10 is connected to described second microprocessor 20 by isolation module；Described first reseting module includes the first transmission reseting module 14, described isolation module includes isolating circuit module 41 and isolation communication module 40, described second reseting module includes the second reception reseting module 26, described first sends reseting module 14 is connected to described second reception reseting module 26 by isolation circuit module 41, and described first communication module 13 is connected to described second communication module 23 by isolation communication module 40；Described first reseting module also includes the first reception reseting module 16, and described watchdog module receives reseting module 16 by described first and is connected to described first main control module 11.
In the present embodiment, described first microprocessor 10 is connected with described watchdog module 30, isolation communication module 40 and isolation circuit module 41 respectively, and described first microprocessor 10 comprises the first main control module 11, first communication module 13, first sends reseting module 14, first timer module 15, feed Canis familiaris L. module 12 and first receives reseting module 16.Described isolation module is the shielding system between first microprocessor 10 and the second microprocessor 20, described first communication module 13 is communicated with described second microprocessor 20 by isolation communication module 40, if first microprocessor 10 does not receives the communication data of the second microprocessor 20 at the appointed time, then first microprocessor 10 sends reset signal by isolation circuit module 41 to the second microprocessor 20, makes the second microprocessor 20 reset.
Described first main control module 11 sends reseting module 14, first timer module 15 for controlling first communication module 13, first, feeds Canis familiaris L. module 12 and first and receive the co-ordination between reseting module 16.Described first communication module 13 is connected with the first main control module 11 and isolation communication module 4 respectively, it is achieved the communication function between first microprocessor 10 and the second microprocessor 20.Described first sends reseting module 14 is connected with the first main control module 11, isolation circuit module 41, respectively for sending reset signal to the second microprocessor 20.When first microprocessor 10 has been received by the communication data of the second microprocessor 20 at the appointed time, then the first transmission reseting module 14 is not to 20 reset signals of the second microprocessor, and the second microprocessor 20 continues normally to work.If first microprocessor 10 does not receives the communication data of the second microprocessor 20 at the appointed time, then the first transmission reseting module 14 sends reset signal to the second microprocessor 20, makes the second microprocessor 20 reset.
Described first timer module 15 is connected with the first main control module 11, it is achieved timing function, so that it is determined that first microprocessor 10 receives the signal of communication of the second microprocessor 20 the most at the appointed time.Described Canis familiaris L. module 12 of feeding is connected with the first main control module 11 and watchdog module 30 respectively, feeding-dog signal is sent to watchdog module 30, i.e. carry out watchdog module 30 feeding Canis familiaris L., according to this signal, watchdog circuit determines whether that first microprocessor 10 sends reset signal.Described first receives reseting module 16 is connected with the first main control module 11 and watchdog module 30, respectively for receiving the reset signal that watchdog module 30 sends.Described watchdog module 30 is connected with described first microprocessor 10, first microprocessor 10 is resetted, if watchdog module 30 has been received by the feeding-dog signal that first microprocessor 10 sends at the appointed time, then watchdog module 30 does not sends reset signal to first microprocessor 10, and first microprocessor 10 continues normally to work；If watchdog circuit 11 does not receives the feeding-dog signal that first microprocessor 10 sends at the appointed time, then watchdog circuit 11 sends reset signal to first microprocessor 10, first microprocessor 10 is resetted, makes first microprocessor 10 internal processes rerun.
Described second microprocessor 20 is connected with described isolation communication module 40 and isolation circuit module 41 respectively.If first microprocessor 10 has been received by the communication data of the second microprocessor 20 at the appointed time, then first microprocessor 10 does not sends reset signal to the second microprocessor 20, and the second microprocessor 20 continues normally to work；If the second microprocessor 20 does not sends communication data to first microprocessor 10, then first microprocessor 10 sends reset signal by isolation circuit module 41 to the second microprocessor 20, makes the second microprocessor 20 reset.
Described second main control module 21 is connected with described second communication module 23 and the second reception reseting module 26 respectively, receives the co-ordination between reseting module 26 for controlling second communication module 23 and second.Described second communication module 23 is connected with the second main control module 21 and isolation communication module 40 respectively, for realizing the communication function between the second microprocessor 20 and first microprocessor 10.Described second receives reseting module 26 is connected with the second main control module 21 and isolation circuit module 41, respectively for receiving the reset signal that first microprocessor 10 sends.Described isolation communication module 40 is connected with described first microprocessor 10 and the second microprocessor 20 respectively, has been used for the mutual transmission of communication data between first microprocessor 10 and the second microprocessor 20.Described isolation circuit module 41 is connected with described first microprocessor 10 and the second microprocessor 20 respectively, for transmitting the reset signal that first microprocessor 10 sends to the second microprocessor 20.
Embodiment 3:
As shown in Figure 4, the present embodiment provides a kind of multi-micro processor system resetting means, at least include first microprocessor 10 and the second microprocessor 20, described first microprocessor 10 includes the first main control module the 11, first reseting module and first communication module 13, and described first reseting module is connected with described first main control module 11 respectively with first communication module 13；Described second microprocessor 20 includes the second main control module the 21, second reseting module and second communication module 23, and described second reseting module is connected with described main control module respectively with second communication module 23；Realizing the transmission of reset signal between described first reseting module and the second reseting module, described first communication module 13 is connected with second communication module 23.
As different from Example 1, as shown in Figure 4, first reseting module described in the present embodiment includes that the first reception reseting module 16 and first sends reseting module 14, described second reseting module includes that the second reception reseting module 26 and second sends reseting module 24, described first receives reseting module 16 is connected with described second transmission reseting module 24, and described first sends reseting module 14 is connected with described second reception reseting module 26；It is worth mentioning that, as shown in Figure 4, described first communication module 13 preferably includes the first signal transmitting module 131 and secondary signal receiver module 132, described second communication module 23 includes secondary signal sending module 231 and secondary signal receiver module 232, described first signal transmitting module 131 is connected with described secondary signal receiver module 232, and described secondary signal receiver module 132 is connected with described secondary signal sending module 231.
In the present embodiment, first microprocessor 10 is connected with the second described microprocessor 20, comprises first main control module the 11, first signal transmitting module the 131, first signal receiving module 132, first and sends reseting module the 14, first reception reseting module 16.If first microprocessor 10 has been received by the correct indication signal of the second microprocessor 20, then first microprocessor 10 is not to 20 reset signals of the second microprocessor, and the second microprocessor 20 continues normally to work.If first microprocessor 10 does not receives the correct indication signal of the second microprocessor 20, then first microprocessor 10 sends reset signal to the second microprocessor 20, makes the second microprocessor 20 reset, so that the second microprocessor 20 internal processes reruns.
Described first main control module 11 sends reseting module 14 with first described signal transmitting module the 131, first signal receiving module 132, first respectively and the first reception reseting module 16 is connected, and receives the co-ordination between reseting module 16 for controlling first signal transmitting module the 131, first signal receiving module the 132, first transmission reseting module 14 and first.Described first signal transmitting module 131 is connected with the first main control module 11 and secondary signal receiver module 232 respectively, and for sending indication signal to the second microprocessor 20, if this signal is normal, then explanation first microprocessor 10 normally works；If this signal is abnormal, then explanation first microprocessor 10 the most normally works.Described first signal receiving module 132 is connected with the first main control module 11 and secondary signal sending module 231 respectively, for receiving the indication signal that the second microprocessor 20 sends, if this signal is normal, then illustrates that the second microprocessor 20 normally works；If this signal is abnormal, then illustrate that the second microprocessor 20 the most normally works.
Described first sends reseting module 14 is connected with the first main control module 11 and the second reception reseting module 26 respectively, for sending reset signal to the second microprocessor 20, if first microprocessor 10 has been received by the correct indication signal of the second microprocessor 20, then first microprocessor 10 is not to 20 reset signals of the second microprocessor, and the second microprocessor 20 continues normally to work；If first microprocessor 10 does not receives the correct indication signal of the second microprocessor 20, then first microprocessor 10 sends reset signal to the second microprocessor 20, makes the second microprocessor 20 reset.Described first receives reseting module 16 is connected, for receiving the reset signal that the second microprocessor 20 sends with the first main control module 11 and the second transmission reseting module 24 respectively.
Described second microprocessor 20 is connected with described first microprocessor 10, comprises the second main control module 21, secondary signal sending module 231, secondary signal receiver module the 232, second transmission reseting module 24 and the second reception reseting module 26.If the second microprocessor 20 has been received by the correct indication signal of first microprocessor 10, then the second microprocessor 20 is not to 10 reset signals of first microprocessor, and first microprocessor 10 continues normally to work；If the second microprocessor 20 does not receives the correct indication signal of first microprocessor 10, then the second microprocessor 20 sends reset signal to first microprocessor 10, makes first microprocessor 10 reset.
Described second main control module 21 sends reseting module 24 with described secondary signal sending module 231, secondary signal receiver module 232, second respectively and the second reception reseting module 26 is connected, and for controlling secondary signal sending module 231, secondary signal receiver module the 232, second transmission reseting module 24 and second receives the co-ordination between reseting module 26.Described secondary signal sending module 231 is connected with the second main control module 21 and the first signal receiving module 132 respectively, for sending indication signal to first microprocessor 10, if this signal is normal, then illustrates that the second microprocessor 20 normally works；If this signal is abnormal, then illustrate that the second microprocessor 20 the most normally works.Described secondary signal receiver module 232 is connected with the second main control module 21 and the first signal transmitting module 131 respectively, and for receiving the indication signal that first microprocessor 10 sends, if this signal is normal, then explanation first microprocessor 10 normally works；If this signal is abnormal, then explanation first microprocessor 10 the most normally works.
Described second sends reseting module 24 is connected with the second main control module 21 and the first reception reseting module 16, for sending reset signal to first microprocessor 10, if the second microprocessor 20 has been received by the correct indication signal of first microprocessor 10, then the second microprocessor 20 is not to 10 reset signals of first microprocessor, and first microprocessor 10 continues normally to work；If the second microprocessor 20 does not receives the correct indication signal of first microprocessor 10, then the second microprocessor 20 sends reset signal to first microprocessor 10, makes first microprocessor 10 reset.Described second receives reseting module 26 is connected, for receiving the reset signal that first microprocessor 10 sends with the second main control module 21 and the first transmission reseting module 14 respectively.
Embodiment 4:
The present embodiment also provides for a kind of monitor, the hardware board of described monitor includes the multi-micro processor system resetting means as described in embodiment 1 to embodiment 3 any one, it is possible to realize taking full advantage of existing resource, Rational Simplification circuit and the technique effect provided cost savings.
The detailed description of the invention of the above is better embodiment of the present utility model; not limit with this and of the present utility model be embodied as scope; scope of the present utility model includes being not limited to this detailed description of the invention, and the equivalence change that all shapes according to this utility model, structure are made is all in protection domain of the present utility model.
Claims (10)
1. a multi-micro processor system resetting means, it is characterized in that, at least including first microprocessor and the second microprocessor being in communication with each other connection, described first microprocessor includes that the first main control module and the first reseting module, described first reseting module are connected with described first main control module；Described second microprocessor includes that the second main control module and the second reseting module, described second reseting module are connected with described main control module；A reseting module in described first reseting module and the second reseting module at least includes the transmission reseting module for sending reset signal, and another reseting module at least includes the reception reseting module for receiving reset signal.
Multi-micro processor system resetting means the most according to claim 1, it is characterised in that described multi-micro processor system resetting means includes at least two microprocessor, between two adjacent microprocessors, cascade connects.
Multi-micro processor system resetting means the most according to claim 1 and 2, it is characterized in that, described first reseting module includes that the first reception reseting module and first being connected with described first main control module respectively sends reseting module, described second reseting module includes that the second reception reseting module and second being connected with described second main control module respectively sends reseting module, and described first receives reseting module is connected with described second transmission reseting module；Described first sends reseting module is connected with described second reception reseting module.
Multi-micro processor system resetting means the most according to claim 3, it is characterised in that described first microprocessor also includes that first timer module, described first timer module are connected with described first main control module；Described second microprocessor also includes that second timer module, described second timer module are connected with described second main control module.
Multi-micro processor system resetting means the most according to claim 1 and 2, it is characterised in that described first microprocessor also includes feeding Canis familiaris L. module, the watchdog module that described first main control module is externally connected by feeding Canis familiaris L. module.
Multi-micro processor system resetting means the most according to claim 5, it is characterised in that also include isolation module, described first microprocessor is connected to described second microprocessor by isolation module.
Multi-micro processor system resetting means the most according to claim 6, it is characterized in that, described first reseting module includes the first transmission reseting module, described isolation module includes isolating circuit module, described second reseting module includes the second reception reseting module, and described first sends reseting module is connected to described second reception reseting module by isolation circuit module.
Multi-micro processor system resetting means the most according to claim 6, it is characterized in that, described first microprocessor also includes first communication module, described second microprocessor also includes second communication module, described isolation module also includes isolating communication module, and described first communication module is connected to described second communication module by isolation communication module.
Multi-micro processor system resetting means the most according to claim 5, it is characterised in that described first microprocessor also includes that first timer module, described first timer module are connected with described first main control module；Described first reseting module also includes the first reception reseting module, and described watchdog module receives reseting module by described first and is connected to described first main control module.
10. a monitor, it is characterised in that described monitor includes the multi-micro processor system resetting means as described in claim 1 to 9 any one.
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| US11989078B2 (en) | 2021-09-30 | 2024-05-21 | Industrial Technology Research Institute | Vehicle control device and method thereof |
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| WO2020119532A1 (en) * | 2018-12-13 | 2020-06-18 | 中兴通讯股份有限公司 | Processor control method and apparatus, and storage medium |
| CN111324494A (en) * | 2018-12-13 | 2020-06-23 | 中兴通讯股份有限公司 | Processor control method, apparatus and storage medium |
| CN111324494B (en) * | 2018-12-13 | 2023-08-25 | 中兴通讯股份有限公司 | Processor control method, device and storage medium |
| CN111679929A (en) * | 2020-06-03 | 2020-09-18 | 北京经纬恒润科技有限公司 | Control method applied to multi-core heterogeneous system |
| CN113535447A (en) * | 2021-06-30 | 2021-10-22 | 浙江中控技术股份有限公司 | Safety control device with dual-processor structure and implementation method |
| US11989078B2 (en) | 2021-09-30 | 2024-05-21 | Industrial Technology Research Institute | Vehicle control device and method thereof |
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