JPS6295637A - Subroutine module for data flow type machine - Google Patents

Abstract

PURPOSE:To attain a subroutine action SL and a recurrent action with a data flow type machine and at the same time to decrease the hardware quantity of a bus with omission of an extension identifier, by storing previously a data identifier in a stack type memory. CONSTITUTION:This subroutine modulus for a machine having a data flow type architecture is provided with a parameter memory 2 which switches the input and output actions according to an input fluctuation identifier and delivers the parameter value and an internal identifier with the fluctuation identifier used as an address, a numerical data processing part, a stack memory 6 which holds temporarily the internal identifier, a pointer memory 5 which stores the address of the memory 6, an identifier memory 3 which supplies the internal identifier as an address and delivers the next fluctuation identifier and the data on the destination, and a destination memory 4. Then each output is connected to a bus from a selector.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a subroutine module for an electronic computer (machine) having a data flow type architecture.

[Conventional technology]

Conventionally, a module of a y'-tafflo type machine has a FIFO type memory in which the data arrangement is not changed, and uses extended identifiers called colored tokens to perform subroutine operations.

FIG. 6 is a flow diagram showing an example of the operation of a subroutine using this extended identifier. In this case, in addition to the data value required in the normal data flow type, the R brush 1 tip, an extended identifier is also transmitted on the data bus. In the figure, an extended identifier is set in step 61, a subroutine calculation operation is performed in step 62, the extended identifier is determined in step 63, and various calculations (step 64) are performed. Subroutine operations are performed in the same manner at steps 65, 66, and 67.

[Problem that the invention seeks to solve]

The module of the conventional dataflow machine mentioned above is
Since only FIFO type operations are performed, recursive operations such as nested holes are difficult. If extended identifiers are used so that subroutines can be used, there is a drawback that the amount of data bus increases.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a subroutine module for a data flow machine that can easily vary the input/output operations of subroutine operations, and can also perform recursive operations and reduce the amount of hardware required. be.

[Failure to solve the problem]

The subroutine module of the Cheetah 0-type machine of the present invention includes a parameter memory that switches input operation and output operation according to an input variation identifier and outputs a parameter value and an internal identifier using this variation identifier as an address; A processing unit that processes and outputs the input numerical data, a stack memory that temporarily holds the internal identifier, a pointer memory that stores the address of this stack memory, and a processing unit that inputs the internal identifier as an address and processes the next one. It is configured to include an identifier memory and a destination memory that output variable variables and destination data, respectively.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a partial block diagram of a cheetah flow type machine using one embodiment of the present invention. Cheetah flow type machine,
A module 10 is connected to a data bus 30 via a bus module connector 20. This data bus 30
by variable identifier.

Destination data and numerical data are sent. Module 1
0 is switched to input or output depending on the identifier.

The pass module connector 20 includes a gate 11° and a comparator 1.
2. Selectors 13-15 are included.

Destination data from data bus 30 is input to comparator 12, and whether or not to input the data to the module is determined by the module address. Based on this determination, the gate 11 is controlled and the variable identifier and numerical data are supplied to the module 10.

This module 10 includes a processing section 1. Parameter memory 2
．． Identifier memory 3. It includes a destination memory 4. The memory in this module is programmed with some shimmering data.

The variable identifier acts as an address for the parameter memory 2 and causes the parameter value 7 and internal identifier 8 to be output. This internal identifier 8 causes the identifier memory 39 to output new variable identifier 9 destination data after processing from the destination memory 4, and connects it to the data bus 30Ki via the selector 14, 13. The processing section 1 processes and outputs numerical data based on the parameter value 7, and connects it to the data bus 30 via the selector 15. Mossy like this
The output data from bus 10 is returned to data bus 3o through selectors 13-15.

FIGS. 2 and 3 show block diagrams of relevant parts during input and output of the subroutine of this embodiment. In this embodiment, for example, the most significant bit of the variable identifier is rxJ, ro
J allows switching between input and output sides.

In the case of the input side as shown in FIG. 2, the variable identifier is input as an address to the parameter memory 2, and the parameter 7 and internal identifier 8 are output. When the most significant bit of parameter 7 is "1", module lO is switched for subroutine input.

The internal identifier 8 acts as an address for the identifier memory 31 destination memory 4, and causes the new variable identifier 9 destination data to be output. Furthermore, the value of the internal identifier 8 is held in the stack memory 6.

The new variable identifier acts as an address in the pointer memory 5 and causes the stack pointer 9 to be output. This stack pointer 9 is used as an address when inputting the internal identifier 8 into the stack memory 6. Note that the value of the stack pointer 9 in the stack memory 6 is incremented to "+1" after the pointer is output in preparation for the next input.

Next, in the case of the output side as shown in FIG. 3, the variable identifier is input as an address to the parameter memory 2, and the parameter 7 and internal identifier 8 are output. When the most significant bit of parameter 7 is "0", module 10 is switched for subroutine output. The internal identifier 8 acts as an address in the pointer memory 5 and causes the stack pointer 9 to be output. This stack void 9 acts as an address in the stack memory 6, and causes the data of the internal identifier 8 that was input at the time of inputting the subroutine to be output. After the pointer is output, the value of the stack pointer 9 is decremented to "-1" in preparation for the next input. The output of this stack memory 6 acts as an address for the identifier memory 31 destination memory 4, and outputs new variable identifier 9 destination data.

FIG. 4 is a flow diagram of an example of subroutine operation using this embodiment. First, in step 41, for example, the variable identifier r001J, the internal identifier "001", the destination data "subroutine module", and the stack pointer "001→
002", and the variation identifier r OO
2J, the destination data becomes the "addition module", and subroutine operations such as addition are performed in step 42. When this subroutine operation is completed, in step 43, the variable identifier ro03J is used, and the internal identifier r002. J, destination data “subroutine module”, stack pointer “0”
02→001", and the fluctuation identifier r
004 J, the destination data becomes "multiplication module" and the next operation is performed in step 44. Thereafter, an input operation of the subroutine module is performed in step 45, a subroutine calculation is performed in step 46, an output operation is performed in step 47, and the process moves to the next operation.

FIG. 5 is a flow diagram of an example of recursive operation performed using the subroutine module of this embodiment.

As in the case of FIG. 4, first, in step 51, the input operation of the subroutine module is performed, and the recursive routine A is selected, and in step 50, the recursive operation of the recursive routine (A) is started. When this recursive operation is completed, an output operation is performed in step 52, and the process moves to the next operation. This recursive routine A
First, a determination process is performed in step 53 to determine whether the input data value is 1, and if the data value is 1, the recursive operation ends. This data value is “1”
'', the data value is set to ``-1'' in the addition process in step 54, and the subroutine input operation is performed in step 55. In step 56, the recursive routine is executed at the data value (n-1).

When this recursive routine is completed, the subroutine output operation occurs in step 57, and the identifier held on this output side is multiplied by "x2" in step 58, and step 5
At step 9, "+" is added and the recursive routine is exited.

〔Effect of the invention〕

As explained above, by storing data identifiers in the memory of the stack shop, the present invention can be used to perform subroutine operations and recursive operations on a data flow type machine, and can be further expanded. It has the advantage that the amount of bus hardware can be reduced because no identifier is required.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data flow type machine including an embodiment of the present invention, FIGS. 2 and 3 are block diagrams of related parts when this embodiment is on the input side and output side, and FIG. FIG. 5 is a flowchart explaining the operation of this embodiment, FIG. 5 is a flowchart of recursive operation of this embodiment, and FIG. 6 is a flowchart of an example of a conventional data flow type machine. 1... Processing section, 2... Parameter memo 1c, 3... Identifier memory, 4... Destination memory, 5... Pointer memory, 6... ...Stack memory, 7...Parameter, 8...
...Internal identifier, 9...Stack pointer, 1
0P... Subroutine module, 11°°. °゛°°Gate 2゛°゛°°° Comparator, 13 to 15...
... Selector, 20 ... Bus fist module connector, 30 ... Data bus, 41 to 47.5
0~59.61~67...Movement step. Mu;'・2 Agents Patent Attorney Uchihara Hi,・1, Kaya L
Closed $ 2 Figure half 3 Seki Figure 5

Claims (1)

[Claims] a parameter memory that switches input operation and output operation according to an input variation identifier and outputs a parameter value and an internal identifier using this variation identifier as an address; and a processing section that processes and outputs input numerical data based on the parameter value. , a stack memory that temporarily holds the internal identifier, a pointer memory that stores the address of this stack memory, and an identifier memory and destination that input the internal identifier as an address and output the next variable variable and destination data, respectively. A module for subroutines in dataflow machines, including memory.