JPS6294955A - Element isolation - Google Patents

Abstract

PURPOSE:To obtain a flat construction by a method wherein a deposit is placed only on the sidewalls of trenches and the trenches are embedded from their both sides by combining a plasma CVD method having a good step coating property with a reactive ion etching technique capable of vertically etching. CONSTITUTION:A resist pattern to form trench isolating regions therein is formed and thereafter, a silicon nitride film 13, a silicon oxide film 12 and a silicon substrate 11 are etched in a vertical state using a reactive ion etching technique. By this way, trenches 4 having a depth of about 5mum are formed. After a resist film is removed, a thermal oxide film 15 and a silicon oxide film 16 are continuously formed. Then, silicon tetrachloride-oxygen mixed gas is introduced in a parallel plate plasma etchign device and pressure is set at 3-5Pa. At the time of high-frequency power =0.05W/cm<2> and the flow rate ratio of SiCl4/H2=1-2, the film thickness of an amorphous silicon film in the vertical direction becomes zero. When a plasma discharge is generated using these conditions, the trenches can be filled almost flatly and completely with an amorphous silicon film 17 deposited from the sidewalls of the trenches.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for isolating elements in a semiconductor device, and particularly to a method for embedding in a trench in trench isolation.

[Conventional technology]

In order to achieve high integration of devices, it is necessary to miniaturize the patterns of all the components of the device according to the scaling law. However, the selective oxidation method (LOG
O8) causes a phenomenon called bird's beak in which the oxide film digs into the element region, making it difficult to form a fine element isolation of 2 μm or less. Therefore, a trench isolation method was proposed in which a vertical trench with a fine width is formed in a silicon substrate, an insulating film is completely formed on the trench wall, and then the inside of the trench is filled with polycrystalline silicon or an insulating film ( Japanese Journal of Agelide Phys4yx, (Japan, J, Appl@Phys, 5
upp1. .

21-1, 37, 1982)).

[Problem that the invention seeks to solve]

In order to fill trenches with a fine width evenly, LPCVD (Low Pressure Chemistry), which has excellent step coverage, is used.
The chemical vapor deposition (mical vapor deposition) method is generally used to deposit polycrystalline silicon over the entire surface with a film thickness approximately equal to the width of the trench. Thereafter, when the entire polycrystalline silicon is uniformly etched and mapped using a reactive ion etching method that strongly etches in the vertical direction, the polycrystalline silicon remains only in the grooves. Further, by thermal oxidation, only the surface of the polycrystalline silicon is oxidized, and a field region is formed. In this way, the conventional method requires a two-step process of film deposition and etching to fill the trench with polycrystalline silicon, and in addition, when etching back, the entire etching must be done so that all of the polycrystalline silicon remains only within the trench. There was a defect in controllability (C).

An object of the present invention is to provide a method for forming element isolation that completely solves these problems.

[Means to solve all problems]

The gist of the present invention is that a gas of a halogenated compound, a hydrogenated compound containing an element to be deposited in a parallel plate plasma etching apparatus, and a gas or hydrogen gas? At least a mixed gas added? introduced,
Plasma discharge is carried out under conditions where the deposition rate of the thin film of the element to be deposited is completely equal to the rate of direct etching of the deposit, and the deposit is buried only in the l-trench.

That is, the present invention is characterized in that plasma CVD with excellent coverage and vertical etching are performed simultaneously and in a well-balanced manner in a plasma apparatus, thereby depositing deposits only on the side walls of the trench and filling the trench from both sides. .

[For production]

The principles of the present invention are explained in Figures 2 to 3 (a), (b) and (e).
Explain using. Figure 2 shows silane tetrachloride (S 1C6
This figure shows the relationship between the mixing ratio of hydrogen and the silicon deposition rate in a mixed gas of 4) and hydrogen, and when the substrate temperature is 2.
The results at 5°C and 200°C are compared. When hydrogen is low, silicon is easily etched by chlorine ions decomposed by plasma discharge, and as hydrogen increases, chlorine ions combine with hydrogen and are exhausted, so silicon begins to accumulate. In Fig. 2, the area where the deposition rate is around zero is expressed as B, and the area of film deposition is expressed as C, where A, B,
The schematic shapes of each C are shown in cross-sectional views in FIGS. 3(a) and (bMc).

101U silicon substrate, 102 silicon oxide film, 10
3 shows the opening of the silicon oxidation hole;
In the area of A shown in a), the silicon substrate itself, D-1:, 77'', as shown in 104, is generated, and as shown in FIG.
In the region C shown in FIG.
Since uniform film deposition and vertical etching occur in balance, the silicon film 105 is deposited only on the sidewalls of the steps. If this state continues, the side wall deposits will come into contact with each other, and the opening will be almost completely buried.

In addition, silane dichloride (S' H2
When CZ 2 ) 2 is used, film deposition is stimulated without adding hydrogen, so the deposition rate can be brought to zero by adding all chlorine gases at the same time.

〔Example〕

Hereinafter, the present invention will be fully explained with reference to the illustrated embodiments, and FIG.
a do d) l″tt trench isolation n-channel MO8
FIG. 3 is a schematic cross-sectional view of the FET cDIA manufacturing process t/i.

400X thermal oxide film 12 and i on p-type silicon substrate 11
After forming a silicon nitride film 13 of 000X and forming a resist pattern for forming a trench isolation region, the silicon nitride film, silicon oxide film, and substrate silicon are vertically etched using reactive ion etching technology using the resist as one mask. Etching. In this way, a trench 14 having a depth of approximately 5 mm is formed. After completely removing the resist film,
15 thermal oxide film 1000X and 16 silicon nitride film 5
00 and increase the pressure to 3-5P.
Set to a. The flow rate ratio between 5tct4 and H2 depends on the input high frequency power, but when the high frequency power is 0.05 W/cm'' and the flow rate ratio is 5ict4/H2 = 1 to 2, the amorphous silicon film thickness in the vertical direction is approximately When plasma emission tk is generated using these conditions, the amorphous silicon 17 deposited from the sidewalls of the trench can fill the trench almost flatly and completely, and is not deposited in other areas at all. The state is shown in Fig. 1(b).When the silicon nitride film 13 on the wide isolation region is removed using ordinary photolithography and thermal oxidation is applied, the silicon nitride film 13 on the wide isolation region and the filled trench is removed. A silicon oxide film 18 with a thickness of about 500X is formed and becomes a field oxide film.Since the trench sidewall is coated with the silicon nitride film 16, no bird's peak occurs in the field oxide film. ) structure is obtained.Next, silicon nitride film 1
After removing the thermal oxide film 12 from the entire surface and forming a dirt oxide film 19 again, an n-channel MO8FET' is manufactured using a normal polycrystalline silicon dirt process, resulting in the structure shown in FIG. 1(d). . Here, there is a polycrystalline silicon gate electrode 20, a source/drain diffusion region 21 formed by arsenic ion implantation, and an interlayer insulating film? 22. Contact hole 2
3. Shown as 24 on aluminum wiring electrode. It was confirmed through electrical measurements that the MOS device thus obtained exhibited good characteristics.

In this example, a mixed system of 5tcz4 and H2 was used, but
A similar effect can also be obtained using a mixed system of S + H4 and at2.

〔Effect of the invention〕

In this way, the present invention utilizes plasma CVD with good step resistance.
Since this method is a combination of etching and reactive ion etching that allows vertical etching, it is possible to fill trenches evenly even in large trenches. Also,
Since the high frequency power used in the plasma discharge of the present invention is about one-tenth or less of the high frequency power input during bias sputtering, damage to the element due to ion bombardment is extremely small and does not pose a substantial problem.

The present invention also has two major advantages over conventional methods. The first is high process tolerance. In other words, the shape of the filled deposit remains unchanged even after the trench is exactly filled by sidewall deposition, and the shape of the filled deposit remains unchanged even after about twice as much time as 9 hours, so that the uniformity within the trench 1 is very good. Conventional etch-back processes are sensitive to trench filling and film thickness, resulting in poor uniformity within the wafer. Second, since the n-circle material filled on the trench is low-density amorphous silicon containing 20 to 30% hydrogen, hydrogen is released during surface oxidation and the volume expansion of the thermal oxide film is small. Therefore, the stress on the element active region on the silicon substrate is reduced and the characteristics of the element are improved. Conventionally, when filled with polycrystalline silicon, a thermal oxide film of 40001 or more causes stress in the substrate and causes stacking faults.

In the present invention, parameters such as high frequency power, discharge pressure, type of gas, and mixing ratio can be changed independently, so optimization of conditions can be easily found, and the lateral deposition rate can also be adjusted from 10 to 100100 nm. ') It has the advantage of being freely variable.

Furthermore, since the present invention can be carried out at temperatures ranging from room temperature to 300 DEG C., it is obvious that it can be applied to wiring of semiconductor devices using semiconductors other than S1, such as 1-2 compounds such as GaAs.

[Brief explanation of drawings]

Figure 1 (a and d) shows an n-channel M with trench isolation.
A schematic cross-sectional view showing the manufacturing process in order of steps using O6FET as an example. Figure 2 shows the relationship between H2 concentration and silicon deposition rate in a 5tcz4 and H2 mixed system. Figure 3 shows the fc principle graph. (bL (cl corresponds to the etching region A, balance region B, and film deposition region C in FIG. 2)) Each shows a schematic cross-sectional view showing a turn shape. 11.101...Silicon substrate; 12. 15.102
...Silicon thermal oxide film, 13.16...Silicon nitride film, 14...Silicon substrate trench, 103...
- Opening of silicon oxide film, 104... Etched surface of silicon substrate, 17, 105... Amorphous silicon deposited on side wall portion, 106... Amorphous silicon deposited on the entire surface, 18... Field Oxide film, 19... Gate oxide film, 20... Polycrystalline silicon gate electrode, 21
... Source/drain diffusion region, 22... Interlayer insulating film, 23... Contact hole, 24... Aluminum wiring electrode.

Claims (1)

[Claims] (1) In a method of forming an element isolation region of a semiconductor device by trench isolation, a gas of a halogenated compound or a hydride compound containing the element to be deposited and a halogen gas or hydrogen gas are mixed in a parallel plate plasma etching apparatus. A gas mixture added at least is introduced, and plasma discharge is performed under conditions that equalize the deposition rate of the thin film of the element to be deposited and the rate of vertical etching of the deposited film, thereby depositing the deposit only in the trench. An element isolation method characterized by embedding.