JPS6294642U - - Google Patents
Info
- Publication number
- JPS6294642U JPS6294642U JP18753685U JP18753685U JPS6294642U JP S6294642 U JPS6294642 U JP S6294642U JP 18753685 U JP18753685 U JP 18753685U JP 18753685 U JP18753685 U JP 18753685U JP S6294642 U JPS6294642 U JP S6294642U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- package body
- semiconductor
- connection terminals
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims 1
- 229910001285 shape-memory alloy Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第1図、第2図は本考案の実施例のフレームの
上面図である。第3図は本考案の実施例のフレー
ムと接続端子の斜視図である。第4図は本考案の
実施例の半導体パツケージ内の斜視図である。第
5図は本考案の実施例の両面回路基板と半導体装
置の斜視図である。第6図は本考案の実施例の両
面回路基板と半導体装置の断面図である。
1,2……フレーム、3,4……突片、5……
接続端子、8……両面回路基板。
1 and 2 are top views of the frame of the embodiment of the present invention. FIG. 3 is a perspective view of the frame and connection terminals of the embodiment of the present invention. FIG. 4 is a perspective view of the interior of a semiconductor package according to an embodiment of the present invention. FIG. 5 is a perspective view of a double-sided circuit board and a semiconductor device according to an embodiment of the present invention. FIG. 6 is a sectional view of a double-sided circuit board and a semiconductor device according to an embodiment of the present invention. 1, 2...Frame, 3, 4...Protrusion, 5...
Connection terminal, 8...Double-sided circuit board.
Claims (1)
本体と、この半導体パツケージ本体の外部に形成
された複数の接続端子と、からなる半導体装置に
おいて、前記接続端子は一定の間隔を有し、所定
の方向に沿つて、2列に配設され、前記間隔は両
面に回路パターンが形成された基板を狭持でき得
る寸法に設定されていることを特徴とする半導体
装置。 (2) 2列の前記接続端子のうち少なくとも一方
の列の前記接続端子の材料として形状記憶合金を
用いることを特徴とする実用新案登録請求の範囲
第(1)項記載の半導体装置。 (3) 前記半導体パツケージ本体は、実質的には
直方体であり、その4つの側端面のうち、少なく
とも2つの側端面に前記接続端子が配設されたこ
とを特徴とする実用新案登録請求の範囲第(1)項
または第(2)項記載の半導体装置。[Claims for Utility Model Registration] (1) In a semiconductor device comprising a semiconductor package body in which a semiconductor element is housed, and a plurality of connection terminals formed outside the semiconductor package body, the connection terminals have a certain number of connections. 1. A semiconductor device, wherein the semiconductor device is arranged in two rows along a predetermined direction with an interval, and the interval is set to a size that can sandwich a substrate having a circuit pattern formed on both sides. (2) The semiconductor device according to claim 1, wherein a shape memory alloy is used as a material for at least one row of the connecting terminals among the two rows of the connecting terminals. (3) The scope of the utility model registration claim, characterized in that the semiconductor package body is substantially a rectangular parallelepiped, and the connection terminals are disposed on at least two of its four side end faces. The semiconductor device according to item (1) or item (2).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18753685U JPS6294642U (en) | 1985-12-05 | 1985-12-05 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18753685U JPS6294642U (en) | 1985-12-05 | 1985-12-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6294642U true JPS6294642U (en) | 1987-06-17 |
Family
ID=31138086
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18753685U Pending JPS6294642U (en) | 1985-12-05 | 1985-12-05 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6294642U (en) |
-
1985
- 1985-12-05 JP JP18753685U patent/JPS6294642U/ja active Pending
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