JPS6294640U - - Google Patents

Info

Publication number
JPS6294640U
JPS6294640U JP18557485U JP18557485U JPS6294640U JP S6294640 U JPS6294640 U JP S6294640U JP 18557485 U JP18557485 U JP 18557485U JP 18557485 U JP18557485 U JP 18557485U JP S6294640 U JPS6294640 U JP S6294640U
Authority
JP
Japan
Prior art keywords
electrode
semiconductor chip
electrode structure
chip carrier
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18557485U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18557485U priority Critical patent/JPS6294640U/ja
Publication of JPS6294640U publication Critical patent/JPS6294640U/ja
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案による電極構造を有するチツプ
キヤリアの一実施例を示す斜視図、第2図は第1
図のチツプキヤリアを反転させて裏面を示した斜
視図、第3図は従来のチツプキヤリアの斜視図、
第4図は従来のチツプキヤリアの断面図である。 1……チツプキヤリア、2……半導体チツプ、
3,3a〜3d……側面電極、4……ワイヤ、5
……パターン、6,6a〜6c……下部電極。
FIG. 1 is a perspective view showing an embodiment of a chip carrier having an electrode structure according to the present invention, and FIG.
Figure 3 is a perspective view of the back side of the chip carrier shown in the figure after being reversed; Figure 3 is a perspective view of the conventional chip carrier;
FIG. 4 is a sectional view of a conventional chip carrier. 1...Chip carrier, 2...Semiconductor chip,
3, 3a to 3d...Side electrode, 4...Wire, 5
...Pattern, 6,6a-6c...lower electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体チツプを乗せ該半導体チツプと基板とを
接続する複数の電極を有するチツプキヤリアの電
極構造において、前記電極の面積を該電極を流れ
る電流量が多いほど大きくなるように定めたこと
を特徴とするチツプキヤリアの電極構造。
An electrode structure of a chip carrier having a plurality of electrodes for mounting a semiconductor chip and connecting the semiconductor chip and a substrate, characterized in that the area of the electrode is set to increase as the amount of current flowing through the electrode increases. electrode structure.
JP18557485U 1985-12-03 1985-12-03 Pending JPS6294640U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18557485U JPS6294640U (en) 1985-12-03 1985-12-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18557485U JPS6294640U (en) 1985-12-03 1985-12-03

Publications (1)

Publication Number Publication Date
JPS6294640U true JPS6294640U (en) 1987-06-17

Family

ID=31134329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18557485U Pending JPS6294640U (en) 1985-12-03 1985-12-03

Country Status (1)

Country Link
JP (1) JPS6294640U (en)

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