JPS6294399U - - Google Patents

Info

Publication number
JPS6294399U
JPS6294399U JP18652385U JP18652385U JPS6294399U JP S6294399 U JPS6294399 U JP S6294399U JP 18652385 U JP18652385 U JP 18652385U JP 18652385 U JP18652385 U JP 18652385U JP S6294399 U JPS6294399 U JP S6294399U
Authority
JP
Japan
Prior art keywords
adder
input signal
delay circuit
reverberation adding
adding circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18652385U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18652385U priority Critical patent/JPS6294399U/ja
Publication of JPS6294399U publication Critical patent/JPS6294399U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の残響付加回路の一実施例の
ブロツク図、第2図は同上残響付加回路の時間対
出力特性図、第3図は従来の残響付加回路のブロ
ツク図、第4図は第3図の残響付加回路の時間対
出力特性を示す図である。 1……入力端子、2……加算器、3……出力端
子、4……遅延回路、5……乗算器、6……変調
入力端子。
Fig. 1 is a block diagram of an embodiment of the reverberation adding circuit of this invention, Fig. 2 is a time vs. output characteristic diagram of the same reverberation adding circuit, Fig. 3 is a block diagram of a conventional reverberation adding circuit, and Fig. 4 is a block diagram of an embodiment of the reverberation adding circuit of this invention. FIG. 4 is a diagram showing the time versus output characteristics of the reverberation adding circuit of FIG. 3; 1... Input terminal, 2... Adder, 3... Output terminal, 4... Delay circuit, 5... Multiplier, 6... Modulation input terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号を加算器を通して遅延回路で遅延させ
、この遅延回路の出力を変調信号により変調した
後に、上記加算器で入力信号と加え合わせるよう
にしたことを特徴とした残響付加回路。
A reverberation adding circuit characterized in that an input signal is delayed by a delay circuit through an adder, the output of the delay circuit is modulated by a modulation signal, and then added to the input signal by the adder.
JP18652385U 1985-12-03 1985-12-03 Pending JPS6294399U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18652385U JPS6294399U (en) 1985-12-03 1985-12-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18652385U JPS6294399U (en) 1985-12-03 1985-12-03

Publications (1)

Publication Number Publication Date
JPS6294399U true JPS6294399U (en) 1987-06-16

Family

ID=31136153

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18652385U Pending JPS6294399U (en) 1985-12-03 1985-12-03

Country Status (1)

Country Link
JP (1) JPS6294399U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5229161A (en) * 1975-09-01 1977-03-04 Toshiba Corp Fluorescent x-ray multiplier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5229161A (en) * 1975-09-01 1977-03-04 Toshiba Corp Fluorescent x-ray multiplier

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