JPS6293970A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6293970A JPS6293970A JP60234817A JP23481785A JPS6293970A JP S6293970 A JPS6293970 A JP S6293970A JP 60234817 A JP60234817 A JP 60234817A JP 23481785 A JP23481785 A JP 23481785A JP S6293970 A JPS6293970 A JP S6293970A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- electrode wiring
- contact
- region
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 17
- 238000013459 approach Methods 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 9
- 230000005012 migration Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 239000012141 concentrate Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000499 gel Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
〔発明の技術分野］
本発明は半導体装置に係り、特にいわゆるくし形構造の
絶縁ゲート電界効果ｌ・ランジスタを右する半導体装置
に関する。
〔発明の技術的背景とその問題点〕
従来のＣＭＯ８半導体装置における電極取り出し部にＪ
３けるＰチャンネルの出力バツフ？トランジ支夕を第３
図、第４図に示す。半導体基板２上にはゲート絶縁膜４
を介してゲート電極配線層６が形成されている。ゲート
電極配線層６の平面形状は第３図に承りように手直ライ
ン状であり、かつジクリ゛り形状をしている。グー１〜
電極配線層６はコンタクト８を介して配線層１０に接続
されている。グー１〜絶縁膜４をマスクとした不純物領
域１２．１／１が半導体基板２表面に形成され、不純物
領域１２．１４下の半導体基板２表面はチャネル領域と
なっている。
半導体基板２上のフィールド絶縁膜１６を介してソース
電極配線層１８およびドレイン電極配線ｈ’ｊ ２０が
形成されている。ソース電極配ｔｉ２層１８およびドレ
イン電極配線層２０は共にくし形彫状をしており、その
くし形彫状部分が互いに噛み合うように対置されている
１、ソース電極配線層１８は電８≦１パッド（図示甘ず
）に接続されており、ドレイン電１ｆｉ Ｆｔｉ！ Ｆ
ｉ１層２０は出力パッド（図示せず）に接続されている
。ソース電極配線層１８はコンタクト２２を介して不純
物領域１２に接続されている。トレイン電極配線層２０
はコンタクト２４を介して不純物領１ｉ！１４に接続さ
れている。
かかる従来の半導体装置においては、電流は電源バッド
からソース電極配線層１８に流れ込み、ソース電極配線
層１８のくし形の凸形状部１８ａの各コンタクト２２に
流れ込む。コンタクト２２に流れ込んだ電流は不純物領
ｈｉ１２から、ゲート電極配線層６下のチャネルを通っ
て周囲の不純物領域１４に流れ込み、コンタクト２４か
らドレイン電極配線層２０のくし形の凸形状部２０ａに
流れ出？Ｊ′。流れ出した電流は凸形状部２０ａを流れ
、トレイン電極配線層２０から出力パッドに流れ出ず。
従来の半導体装置では電流がこのように流れるため、ソ
ース電極配線層１８の電源パッドに近い領域のコンタク
ト２２およびドレイン電極配置層２０の出力パッドに近
い領域のコンタク１−２４には大きな電流が集中し、エ
レクトロマイグレーション現象が発生づ−るという問題
があった。、電極配線ＦＪ１８，２０の厚さは配線部分
よりコンタクト部分の段差部分が特に薄くなっているた
め、大きな電界が集中すると、その薄い部分でアルミニ
ウムのマイグレーション現象（電子の移動）が起こリコ
ンタクト部２２．２４と電極配線層１８゜２０とが電気
的に分離された断線状態となる。
ひとつのコンタクトの抵抗が大きくなったり、断線した
すすると、その分の電流が他のコンタク１〜に流れ、そ
のコンタクトｂ不良状態となる。そして時間とともに出
ノｊ電流が減少し最終的には完全断線状態になってしま
う。
このように配線層のアルミニウムのエレク１−［１マイ
グレーシ１ン現象は大電流が流れる電極取り出し部にお
いて信頼性上大きな問題ど１．１っていた。
かかるアルミニウムのエレクＩ−ロマイグレーシ＝ｌン
現象を防止するためには、ソース電極配線層１８および
ドレイン電極配線層２０の凸形状部１８ａ、２０ａを十
分な電流を流すことができるにうに幅広にしなくてはな
らない。幅広に覆ればそれだ[Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a so-called comb-shaped insulated gate field effect transistor. [Technical background of the invention and its problems] J
3rd P channel output buffer? 3rd transition support
It is shown in Fig. 4. A gate insulating film 4 is formed on the semiconductor substrate 2.
A gate electrode wiring layer 6 is formed through the gate electrode wiring layer 6. As shown in FIG. 3, the planar shape of the gate electrode wiring layer 6 is a straight line shape and a rectangular shape. Goo 1~
The electrode wiring layer 6 is connected to the wiring layer 10 via contacts 8. Impurity regions 12.1/1 are formed on the surface of the semiconductor substrate 2 using the insulating films 1 to 4 as masks, and the surface of the semiconductor substrate 2 below the impurity regions 12.14 serves as a channel region. A source electrode wiring layer 18 and a drain electrode wiring h'j 20 are formed on the semiconductor substrate 2 with a field insulating film 16 interposed therebetween. The source electrode wiring layer 18 and the drain electrode wiring layer 20 both have a comb-shaped shape, and are opposed to each other so that the comb-shaped portions interlock with each other. It is connected to the pad (not shown), and the drain voltage is 1fi Fti! F
The i1 layer 20 is connected to an output pad (not shown). Source electrode wiring layer 18 is connected to impurity region 12 via contact 22 . Train electrode wiring layer 20
through the contact 24 to the impurity region 1i! 14. In such a conventional semiconductor device, current flows from the power supply pad into the source electrode wiring layer 18 and into each contact 22 of the comb-shaped convex portion 18a of the source electrode wiring layer 18. The current flowing into the contact 22 flows from the impurity region hi12 through the channel under the gate electrode wiring layer 6 into the surrounding impurity region 14, and flows out from the contact 24 into the comb-shaped convex portion 20a of the drain electrode wiring layer 20? J′. The current flowing out flows through the convex portion 20a and does not flow out from the train electrode wiring layer 20 to the output pad. In conventional semiconductor devices, current flows in this way, so a large current is concentrated in the contacts 22 in the region of the source electrode wiring layer 18 near the power supply pad and in the contacts 1-24 in the region of the drain electrode arrangement layer 20 near the output pad. However, there was a problem in that electromigration phenomenon occurred. The thickness of the electrode wiring FJ18, 20 is particularly thinner at the step part of the contact part than the wiring part, so when a large electric field is concentrated, aluminum migration phenomenon (electron movement) occurs in the thin part and the recontact part 22, 24 and the electrode wiring layer 18.degree. 20 are electrically separated, resulting in a disconnected state. If the resistance of one contact becomes large or the contact becomes disconnected, the corresponding current flows to the other contacts 1 to 1, resulting in the contact b being in a defective state. Then, the output current decreases over time, and eventually the wire becomes completely disconnected. As described above, the electromagnetic migration phenomenon of the aluminum of the wiring layer has caused a serious problem in terms of reliability at the electrode lead-out portion through which a large current flows. In order to prevent such aluminum electromigrain phenomenon, the convex portions 18a and 20a of the source electrode wiring layer 18 and the drain electrode wiring layer 20 are made wide enough to allow a sufficient current to flow. Must-have. That's it if you cover it wide.
【）出力バッファの両トラ
ンジスタのエリア面積が増大し、チップリーイズが大き
くなり、ロス１−アップになるという問題があった。
〔発明の目的〕
本発明は上記事情を元売してなされな乙ので、デツプサ
イズを大きくすることなく特定部分に電流が集中せずア
ルミニウムのエレク：〜１−】マイグレーシー１ンを抑
制し、寿命の良い信頼性ある半導体装置を提供づること
を目的とする。
〔発明の概要〕
」二記目的を達成するために本発明による半導体装置は
、ソース電極配線層およびドレイン電極配線層の凸形状
部の基部を拡大し、噛み台ねりことにより、全体のデツ
プサイズを大きくすることなく、大ぎな電流が流れる部
分の電極配線層を幅広にしたことを特徴と１゛る。
またゲート電極配線層により分離された不純物領域の各
島状領域は、ソース電極配線層およびドレイン電極配線
層が接続されたコンタクト近傍の部分が幅広であること
が望ましい。
また」ンタク１−はソース電極配線層およびドレイン電
極配線層の凸形状部の基部に近くなるほど人さく形成さ
れることが望ましい。
さらに、ゲート電極配線層はジグザグ形状をしており、
このジグザグ形状は、ゲート電極配線層下のヂＰネルγ
１域により分画１された！；、）状領域の面積がソース
およびドレイン電極配ｓ！２層の凸形状部の基部に近く
イ１ろ稈人さく １ＪるＪ、うに変化りるピッチで形成
され℃いることが望ましい。
〔発明の実施例〕
本発明の一実施例によるＣＭＯ３′Ｖ導体装置のＰチャ
ンネル出力バラツノ・１−ランジスタを第１図、第２図
に承り。なお、ｎチャンネルの出力バッフ７１−ノンジ
スタｔま第１図、第２図と対称的な＋ｉ４成であるため
図示を省略した。例えばＮ型の半導体基板５２ Ｊ＝に
は、例えば窒化膜からくべろグーｌ−絶縁膜５４を介し
Ｃ例えばポリシリコンからなるゲート電極配線層５６が
形成されている。グー１へ電極配線層５５６の平面形状
は第１図に示Ｊ Ｊ、・）に従来と同様に垂直ライン状
−Ｃ・あり、ジグザグ形状をし曲がり角が鈍角になって
いるため、グー１〜電極配線層５６が１ｉｉｌ−面積に
、１３いて長くて・き、電流をより多く取る事ができる
。複数のゲル１〜電（＋配線層５６は］ンタクト５８を
介して配線層６０に接続され−Ｃいる。
また半導体基板５２表面にはｐ型の不純物領域６２．６
４が形成されている。この不純物領域６２．６４はグー
１へ絶縁膜５）４のパターンをマスクとして自己整合的
に形成されており、ゲート絶縁膜５４モの半導体基板５
２の表面はｐ ｆ−ｔｒネル領域どなっている。すなわ
ちゲート絶縁膜５４下のｐヂャネル領域により島状の不
純物領域６２゜６４に分離されたことになる。不純物領
域６２はトレイン領域となり、不純１カ領Ｖｉ６４はソ
ース領域となる。
半導体基板５２上のフィールド絶縁膜６Ｇを介してソー
ス電極配線層６８ Ｊ５ Ｊ、びドレイン電極配線層７
０が形成されている。ソース？ｒ２棒配線層６８および
ドレイン電極配線層７０は共に基部が拡大した複数の凸
形状部６８ａ、７０ａを有してよ５つ、これら凸形状部
６８ａと凸形状部７０ａがＨいに噛み合うように対置さ
れている。従来と異なり凸形状部６８ａ、７０ａが基部
に近くなるほど幅広に４ｆつ−Ｃいる点に特徴がある。
従来と同様、ソース電極配線層６８は電源パッド（図示
せず）に接続されこおり、ドレイン電極配線層７０は出
力パッド（図示せず）に接続されている。
ソース電極配線Ｖ４６８は丁１ンタクト７２を介してソ
ース領Ｉ１１！６２に接続されでいる。またドレイン電
極配線層７０はコンタクト７４を介してドレイン領域７
４に接続され又いる。」ンタク１−７２はソース電極配
置！１ｌＡＷ６８の凸形状部Ｇ８ａのＪＡ 八ｌｌに近
くなるほどその平面形状が人さくａっている。
またコンタクト７４−ｂドレイン電極配線位７０の凸形
状部７０ａの基部に近くなろ（，１と−ぞの平面形状が
大きくなっている。
本実施例によれば、電流は電源パッドからソース電極配
線層６８に流れ込み、基部が幅広の凸形状部６８ａに流
れ、各コンタク１−７２に流れ込む。
このとき凸形状部５Ｑａの基部付近は先端よりも多くの
電流が流れる。これは基部付近はど多くのコンタク１−
に流れ込む電流流れ、先端付近になれば【よとんどの°
上流ｔより゛でにその前にあるコンタクトに流れ込んで
いるからである。本実施例ではより多くの電流が流れる
凸形状部６８ａの基部が幅広になっているので、従来の
Ｊ：うに電流が集中づることなく、アルミニウムのエレ
ク１〜ロマイグレーション現やの発生を防止できる。
コンタクト７２に流れ込んだ電流はソース領域６２から
、ゲート電極配線層５６下のｐチャネル領域を通って周
囲のドレイン領Ｖ１．６４に流れ込む。
ドレイン領域６４に流れ込んだ電流はコンタクトを介し
てトレイン電極配線層７０の凸形状部７０ａに流れ出づ
−０流れ出した電流は凸形状部７０ａを流れ、ドレイン
電極配線層７０から出力パッドに流れ出す。このとき凸
形状部７０ａの基部付近は先端よりも多くの電流が流れ
る。これは基部付近はど多くのコンタクｌ−から流れ出
した電流が流れるからである。木実７ＩＩ！！例ではよ
り多くの’＋１ｉ流が流れる凸形状部７Ｑａの基部が幅
広になっているので、従来のように基部付近のコンタク
トに電流が集中することなく、アルミニウムのエレク１
〜ロマイグレーション現象の発生を防止できる。
このように本実施例では凸形状部の基部のコンタク１〜
に電流が集中づることがないのでアルミニ「クムのＪレ
クトロマイグレーシ」ン現象の発生を防止できる。また
、ドレイン゛上極配線層およびソース電極配線層の凸形
状部が噛み合うような形状になっているので、凸形状部
の基部を幅広にしても全体的なチップ面積を増大さＵる
ことがない。
また」ンタク１〜の平面形状も凸形状部の基部に行くほ
ど大きくなっているので、基部を幅広にしてもソース領
域とドレイン領域のコンタクト間の距離が艮くイ１らず
、これら］コンタクト間を流れる電流の抵抗を大きくす
ることがない。
本発明は上記実施例に限定されず種々の変形が可能であ
る。例えば上記実施例では凸形状部の幅が連続的に変化
するように形成されているが、幅が断続的に変化（Ｊ゛
るように階段状の平面形状にしてｂよい。さらにコンタ
ク１〜の平面形状を１−記実施例のように変えることな
く、同一の大きさとしてもよい。ざらにゲート電極配線
層は従来のように直角のジグ瞥アゲ形状でもよく、また
ジグ奢アゲ形状にすることなく直線形状でもよい。
またゲート絶縁膜は窒化膜に限らず酸化膜でもよい。さ
らに上記実施例は０ＭＯ８であったが、ＮＭＯ８にもＰ
ＭＯ８にも本発明を適用できることはいうまでもない。
〔発明の効果〕
以上の通り本発明によればチップ１ノイズを大きくする
ことなく、特定部分に電流が集中しないように構成する
ことができる。したがってアルミニウムのルクトロマイ
グレーション現象等により配線層が劣化して断線状態に
至ることなく、信頼性が向上できる。[) There is a problem that the area of both transistors of the output buffer increases, the chip rise increases, and the loss increases by 1-up. [Object of the Invention] The present invention has been made in consideration of the above-mentioned circumstances, and therefore suppresses the migration of an aluminum electric current without increasing the depth size and preventing current from concentrating on a specific part. The purpose is to provide reliable semiconductor devices with a long life. [Summary of the Invention] In order to achieve the second object, the semiconductor device according to the present invention enlarges the bases of the convex portions of the source electrode wiring layer and the drain electrode wiring layer, and by bending the bases, the overall depth size is reduced. The feature is that the electrode wiring layer in the area where a large current flows is made wider without increasing the size. Further, it is desirable that each island region of the impurity region separated by the gate electrode wiring layer has a wide portion near the contact to which the source electrode wiring layer and the drain electrode wiring layer are connected. Further, it is preferable that the contact 1- is formed more inconspicuously as it approaches the base of the convex portion of the source electrode wiring layer and the drain electrode wiring layer. Furthermore, the gate electrode wiring layer has a zigzag shape,
This zigzag shape is caused by the dinel γ under the gate electrode wiring layer.
It was fractionated by 1 area! The area of the ;,)-shaped region is the source and drain electrode arrangement s! It is desirable that the pitch be formed near the base of the convex portion of the two layers at a pitch that changes from 1 to 1 to 1 to 1. [Embodiment of the Invention] FIGS. 1 and 2 show a P-channel output variable 1-transistor of a CMO 3'V conductor device according to an embodiment of the present invention. Note that since the n-channel output buffer 71 and the non-transistor t have a +i4 configuration symmetrical to those in FIGS. 1 and 2, illustration thereof is omitted. For example, a gate electrode wiring layer 56 made of polysilicon, for example, is formed on an N-type semiconductor substrate 52 J=, with an insulating film 54 ranging from a nitride film interposed therebetween. The planar shape of the electrode wiring layer 556 is shown in FIG. The electrode wiring layer 56 has an area of 13 mm and is long, so that a larger amount of current can be taken. A plurality of gels 1 to 56 are connected to the wiring layer 60 via contacts 58. Also, p-type impurity regions 62.6 are formed on the surface of the semiconductor substrate 52.
4 is formed. These impurity regions 62 and 64 are formed in a self-aligned manner using the pattern of the insulating film 5) 4 as a mask, and are formed on the semiconductor substrate 5 of the gate insulating film 54.
2 has a pf-tr channel region. That is, the p-channel region under the gate insulating film 54 separates the impurity regions into island-like impurity regions 62° and 64. The impurity region 62 becomes a train region, and the impurity region Vi64 becomes a source region. The source electrode wiring layer 68 J5 J and the drain electrode wiring layer 7 are formed on the semiconductor substrate 52 via the field insulating film 6G.
0 is formed. sauce? Both the r2 rod wiring layer 68 and the drain electrode wiring layer 70 have a plurality of convex portions 68a and 70a whose bases are enlarged, and these convex portions 68a and convex portions 70a engage with each other in an H-shaped manner. Opposite. Unlike the conventional structure, the convex portions 68a and 70a are 4f wide as they get closer to the base. As before, the source electrode wiring layer 68 is connected to a power supply pad (not shown), and the drain electrode wiring layer 70 is connected to an output pad (not shown). The source electrode wiring V468 is connected to the source region I11!62 via the contact 72. Further, the drain electrode wiring layer 70 is connected to the drain region 7 through a contact 74.
It is connected to 4. ”Tak 1-72 has a source electrode arrangement! The closer the convex portion G8a of 1lAW68 is to the JA8ll, the more conspicuous its planar shape becomes. In addition, the contact 74-b is located near the base of the convex portion 70a of the drain electrode wiring position 70 (the planar shape of the contacts 74-b and 1) is large. The current flows into the layer 68, flows into the convex portion 68a whose base is wide, and flows into each contact 1-72.At this time, more current flows near the base of the convex portion 5Qa than at the tip. Contact 1-
The current flowing into the
This is because it has already flowed into the contact in front of the upstream t. In this embodiment, since the base of the convex portion 68a through which more current flows is widened, the current does not concentrate as in the conventional case, and the occurrence of aluminum migration can be prevented. . The current flowing into the contact 72 flows from the source region 62 through the p-channel region under the gate electrode wiring layer 56 and into the surrounding drain region V1.64. The current flowing into the drain region 64 flows through the contact into the convex portion 70a of the train electrode wiring layer 70. The current flows through the convex portion 70a and flows out from the drain electrode wiring layer 70 to the output pad. At this time, more current flows near the base of the convex portion 70a than at the tip. This is because current flowing from many contacts l- flows near the base. Kinomi 7II! ! In the example, since the base of the convex portion 7Qa through which more '+1i current flows is wide, the current does not concentrate on the contact near the base as in the conventional case, and the aluminum electric
~The occurrence of romigration phenomenon can be prevented. In this way, in this example, the contacts 1 to 1 at the base of the convex portion are
Since the current is not concentrated on the aluminum plate, it is possible to prevent the aluminum ``Kum J Lectromigration Grain'' phenomenon from occurring. In addition, since the convex portions of the drain/upper electrode wiring layer and the source electrode wiring layer are shaped to mesh with each other, the overall chip area can be increased even if the base of the convex portion is widened. do not have. In addition, the planar shape of contact 1 becomes larger toward the base of the convex portion, so even if the base is made wider, the distance between the contacts in the source region and drain region does not change. It does not increase the resistance of the current flowing between the two. The present invention is not limited to the above embodiments, but can be modified in various ways. For example, in the above embodiment, the width of the convex portion is formed so as to change continuously, but it may be formed into a step-like planar shape so that the width changes intermittently. It is also possible to have the same size without changing the planar shape as in Embodiment 1.Roughly, the gate electrode wiring layer may have a right-angled jig-edge shape as in the conventional case, or it may have a jig-shape shape. In addition, the gate insulating film is not limited to a nitride film, but may also be an oxide film.Furthermore, although the above embodiment was 0MO8, NMO8 and P
It goes without saying that the present invention can also be applied to MO8. [Effects of the Invention] As described above, according to the present invention, it is possible to configure the device so that the current does not concentrate on a specific portion without increasing the chip 1 noise. Therefore, reliability can be improved without deteriorating the wiring layer and causing a disconnection state due to the lutromigration phenomenon of aluminum or the like.
第１図は本発明の一実施例による半導体装置の平面図、
第２図は同半導体装置の八−直線断面図、第３図は従来
の半導体装置の平面図、第４図は同半導体装置のＢ−Ｂ
線断面図である。
２．５２・・・半導体堰板、４，５４・・・ゲート絶縁
膜、６．５６・・・ゲート電極配Ｆｔ１層、８．５８・
・・コンタクト、１０．６０・・・配線層、１２．６２
・・・ソース領域、１４．６４・・・ドレイン領域、１
６゜６６・・・フィールド絶縁膜、１８．６８・・・ソ
ース電極配線層、１８ａ、６８ａ・・・凸形状部、２０
゜７０・・・トレイン電極配線層、２０ａ、７０ａ・・
・凸形状部、２２．７２・・・コンタクト、２Ｃ７／Ｉ
・・・コンタクト。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view along the line 8 of the same semiconductor device, FIG. 3 is a plan view of the conventional semiconductor device, and FIG. 4 is a B-B of the same semiconductor device.
FIG. 2.52...Semiconductor dam plate, 4,54...Gate insulating film, 6.56...Gate electrode arrangement Ft1 layer, 8.58...
...Contact, 10.60...Wiring layer, 12.62
... Source region, 14.64 ... Drain region, 1
6゜66...Field insulating film, 18.68...Source electrode wiring layer, 18a, 68a...Convex shaped portion, 20
゜70...Train electrode wiring layer, 20a, 70a...
・Convex shape part, 22.72...Contact, 2C7/I
···contact.
Claims (1)
、基部が拡大した複数の凸形状部を有する第１の電極配
線層と、 前記半導体基板上に前記フィールド絶縁膜を介して形成
され、前記第１の電極配線層の凸形状部間の凹部にかみ
合う、基部が拡大した複数の凸形状部を有する第２の電
極配線層と、 前記半導体基板上に薄いゲート絶縁膜を介して形成され
、前記第１の電極配線層および前記第２の電極配線層の
凸形状部を横切る複数条のゲート電極配線層と、 前記第１の電極配線層および前記第２の電極配線層の凸
形状部下を含む前記半導体基板表面に形成され、前記ゲ
ート電極配線層下の前記半導体基板表面に形成されたチ
ャネル領域により複数の島状領域に分離された不純物領
域とを備え、 前記第１の電極配線層に前記不純物領域の島状領域がひ
とつおきに第１のコンタクトを介してそれぞれ接続され
、前記第２の電極配線層に前記不純物領域の残りの島状
領域が第２のコンタクトを介してそれぞれ接続されたこ
とを特徴とする半導体装置。 ２、特許請求の範囲第１項記載の装置において、前記不
純物領域の各島状領域は、前記第１の電極配線層および
前記第２の電極配線層が接続された前記第１のコンタク
トおよび前記第２のコンタクト近傍の部分が幅広である
ことを特徴とする半導体装置。 ３、特許請求の範囲第１項又は第２項記載の装置におい
て、前記第１のコンタクトは前記第１の電極配線層の凸
形状部の基部に近くなるほど大きく形成され、前記第２
のコンタクトは前記第２の電極配線層の凸形状部の基部
に近くなるほど大きく形成されていろことを特徴とする
半導体装置。 ４．特許請求の範囲第１項乃至第３項のいずれかに記載
の装置において、前記ゲート電極配線層はジグザグ形状
をしており、このジグザグ形状は、前記チャネル領域に
より分離された島状領域の面積が前記第１及び第２の電
極配線層の凸形状部の基部に近くなる程大きくなるよう
に変化するピッチで形成されていることを特徴とする半
導体装置。[Claims] 1. A semiconductor substrate; a first electrode wiring layer formed on the semiconductor substrate via a field insulating film and having a plurality of convex portions with enlarged bases; a second electrode wiring layer formed through the field insulating film and having a plurality of convex portions with enlarged bases that engage with recesses between the convex portions of the first electrode wiring layer; and on the semiconductor substrate. a plurality of gate electrode wiring layers formed through a thin gate insulating film and crossing the convex portions of the first electrode wiring layer and the second electrode wiring layer; an impurity region formed on the surface of the semiconductor substrate including the convex portion of the second electrode wiring layer and separated into a plurality of island-like regions by a channel region formed on the surface of the semiconductor substrate below the gate electrode wiring layer; Every other island-like region of the impurity region is connected to the first electrode wiring layer via a first contact, and the remaining island-like region of the impurity region is connected to the second electrode wiring layer. A semiconductor device characterized in that these are connected to each other via a second contact. 2. In the device according to claim 1, each island region of the impurity region is connected to the first contact to which the first electrode wiring layer and the second electrode wiring layer are connected; A semiconductor device characterized in that a portion near the second contact is wide. 3. In the device according to claim 1 or 2, the first contact is formed to be larger as it approaches the base of the convex portion of the first electrode wiring layer, and
A semiconductor device characterized in that the contact is formed larger closer to the base of the convex portion of the second electrode wiring layer. 4. In the device according to any one of claims 1 to 3, the gate electrode wiring layer has a zigzag shape, and the zigzag shape has an area of an island region separated by the channel region. is formed at a pitch that changes such that the closer to the base of the convex portion of the first and second electrode wiring layers, the larger the pitch is.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60234817A JPS6293970A (en) | 1985-10-21 | 1985-10-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60234817A JPS6293970A (en) | 1985-10-21 | 1985-10-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6293970A true JPS6293970A (en) | 1987-04-30 |
| JPH0255953B2 JPH0255953B2 (en) | 1990-11-28 |
Family
ID=16976847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60234817A Granted JPS6293970A (en) | 1985-10-21 | 1985-10-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6293970A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008527704A (en) * | 2005-01-06 | 2008-07-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Thin film transistor array device |
| JP2009016686A (en) * | 2007-07-06 | 2009-01-22 | Toshiba Corp | High frequency transistor |
| WO2009022509A1 (en) * | 2007-08-10 | 2009-02-19 | Mitsumi Electric Co., Ltd. | Mos transistor and semiconductor integrated circuit device using the same |
| WO2010070824A1 (en) * | 2008-12-19 | 2010-06-24 | 株式会社アドバンテスト | Semiconductor device, method for manufacturing semiconductor device, and switch circuit |
-
1985
- 1985-10-21 JP JP60234817A patent/JPS6293970A/en active Granted
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008527704A (en) * | 2005-01-06 | 2008-07-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Thin film transistor array device |
| JP2009016686A (en) * | 2007-07-06 | 2009-01-22 | Toshiba Corp | High frequency transistor |
| WO2009022509A1 (en) * | 2007-08-10 | 2009-02-19 | Mitsumi Electric Co., Ltd. | Mos transistor and semiconductor integrated circuit device using the same |
| JP2009044085A (en) * | 2007-08-10 | 2009-02-26 | Mitsumi Electric Co Ltd | Mos transistor and semiconductor integrated circuit device using it |
| WO2010070824A1 (en) * | 2008-12-19 | 2010-06-24 | 株式会社アドバンテスト | Semiconductor device, method for manufacturing semiconductor device, and switch circuit |
| US8466566B2 (en) | 2008-12-19 | 2013-06-18 | Advantest Corporation | Semiconductor device, method for manufacturing of semiconductor device, and switching circuit |
| TWI416704B (en) * | 2008-12-19 | 2013-11-21 | Advantest Corp | Semiconductor device, production method of semiconductor device, and switch circuit |
| JP5656644B2 (en) * | 2008-12-19 | 2015-01-21 | 株式会社アドバンテスト | Semiconductor device, semiconductor device manufacturing method and switch circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0255953B2 (en) | 1990-11-28 |
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