JPS6292989A - Solder plating substrate - Google Patents
Solder plating substrateInfo
- Publication number
- JPS6292989A JPS6292989A JP23391285A JP23391285A JPS6292989A JP S6292989 A JPS6292989 A JP S6292989A JP 23391285 A JP23391285 A JP 23391285A JP 23391285 A JP23391285 A JP 23391285A JP S6292989 A JPS6292989 A JP S6292989A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- terminals
- solder plating
- board
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、液晶表示素子（ＬＣＤ）等の基板として用い
られ、その端子形成部と他の装置の端子形成部とを半田
接続するための半田メッキ用基板に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention is used as a substrate for a liquid crystal display element (LCD), etc., and is used for solder connection between the terminal forming portion of the substrate and the terminal forming portion of another device. The present invention relates to a board for solder plating.
従来、液晶表示素子等の基板におりる端子形成部のファ
インピンチの端子群と、その駆動用ＬＳＩ等の設置用基
板における端子形成部の出力端子群とを接続する場合、
ゴムコネクタ一方式や異方性導電膜方式等が採用される
のが通例である。しかしながら、これらの方法は、高温
高温（６０℃・９５％）や熱サイクル（−４０℃寞１０
０℃）により劣化され易いという欠点があり、必ずしも
電子機器として必要な信顛性を得るには至っていない。Conventionally, when connecting a group of fine-pinch terminals of a terminal forming part on a substrate such as a liquid crystal display element, and a group of output terminals of a terminal forming part of an installation board such as a driving LSI,
Usually, a one-sided rubber connector type or an anisotropic conductive film type is used. However, these methods require high temperatures (60°C, 95%) and thermal cycles (-40°C, 10%).
It has the disadvantage that it is easily deteriorated by temperatures (0°C), and it has not necessarily achieved the reliability required for electronic equipment.
上記の欠点を解決する手段として、半田による接続方法
が考えられ、比較的＄ｌい０．５〜０．６龍ピツチの端
子間の接続については実用化されている。ところが、Ｏ
Ａｉ器、特にハンドベルトコンピュータ等の表示素子と
して用いられる液晶表示素子等は、限られた表示面積で
多くの表示を行う必要があることから、基板上のライン
数も多くなり、従って、端子間ピンチも０．３〜Ｑ、４
ｍｍピッチと小さくなってきている。このファインピッ
チの対応する端子間を接続することを目的として、前記
した半田接続方法を用いる場合には、以下の問題を有し
ている。As a means to solve the above-mentioned drawbacks, a connection method using solder has been considered, and has been put into practical use for connection between terminals of 0.5 to 0.6 pitch, which is relatively expensive. However, O
Ai devices, especially liquid crystal display elements used as display elements for hand belt computers, etc., need to display a large amount of information in a limited display area, so the number of lines on the board increases, and therefore the number of lines between terminals increases. Pinch is also 0.3~Q, 4
The pitch is getting smaller and smaller. When the above-described solder connection method is used for the purpose of connecting between corresponding terminals of this fine pitch, there are the following problems.
（１） 端子上に形成する半田メッキ膜厚を２０μｍ程
度とすると、他の装置の対応端子と接続するときに、隣
り合う端子間で半田のブリッジが生じ短絡のおそれがあ
る。(1) If the thickness of the solder plating film formed on the terminal is about 20 μm, there is a risk that a solder bridge will occur between adjacent terminals and cause a short circuit when connecting to a corresponding terminal of another device.
（２） 半田メッキ膜厚を２〜３μｍ程度にすると、対
応する接続端子間の接合強度が弱くなり実用に耐えられ
ない。(2) When the solder plating film thickness is about 2 to 3 μm, the bonding strength between the corresponding connection terminals becomes weak and cannot be put to practical use.
（３） また、上記欠陥を生じない半田メッキ膜として
、膜厚を１３μｍ程度に設定した場合、メッキ処理に使
用されるパターンメッキ法では、第３図（ａ）に示すよ
うに、５枚の基板１を１セント（１フラツト）にして半
田メッキがなされ、同図斜線部で示すように、端子形成
部３における左右両端部３ａ・３ｂの電流密度が高くな
る。このため、上記左右両端部３ａ・３ｂに形成された
同図（ｂ）の端子群２・２上の半田メッキ膜厚が大きく
なり、他の装置の端子と接続する際、上記端子群２・２
の隣り合う端子間に半田のブリッジが発生し易くなる。(3) In addition, when the film thickness is set to about 13 μm as a solder plating film that does not cause the above defects, the pattern plating method used for plating processing requires five solder plating films as shown in Figure 3 (a). Solder plating is performed with the substrate 1 at 1 cent (1 flat), and the current density at both left and right ends 3a and 3b of the terminal forming portion 3 becomes high, as shown by the shaded area in the figure. For this reason, the thickness of the solder plating on the terminal groups 2 and 2 shown in FIG. 2
Solder bridging is likely to occur between adjacent terminals.
Ｃ発明の目的〕
本発明は、上記従来の問題点を考慮してなされたもので
あって、各端子の半田メッキ膜厚を均一に形成し得るよ
うに構成して、半田接続の際、隣り合う端子間にわたる
半田のブリッジの発生を抑制し、ＬＣＤユニットの信頬
性を向上させた半田メッキ用基板の提供を目的とするも
のである。C. Object of the Invention The present invention has been made in consideration of the above-mentioned conventional problems. The object of the present invention is to provide a solder plating substrate that suppresses the occurrence of solder bridging between mating terminals and improves the reliability of an LCD unit.
本発明に係る半田メブキ用基板は、端子群及び基板の位
置設定用のトンボが形成されている端子形成部上の余白
部のうち、少なくとも上記端子群と、基板の両側位置設
定用のｌ・ンボとの間の余白部にダミー端子を設けて、
各端子上に均一な膜厚の半田メッキ層を形成し得るよう
にしたことを特徴とするものである。The soldering board according to the present invention has at least the terminal group and the margins on the terminal forming part where register marks for positioning the terminal group and the board are formed, and the margins for setting the positions of both sides of the board. Provide a dummy terminal in the margin between the
The present invention is characterized in that a solder plating layer of uniform thickness can be formed on each terminal.
本発明の第１実施例を第１図に基づいて説明すれば、以
下の通りである。The first embodiment of the present invention will be described below based on FIG.
液晶表示素子（ＬＣＤ）の基板１１上には、複数のライ
ン１２・・・が縦縞状に設けられている。基ｖｉ１１の
一端には、端子形成部１３が所定の長さに亘って突出し
た状態に形成されている。この端子形成部１３上には、
上記各ライン１２・・・の端子１２ａ・・・が並列状に
形成され、これにより端子群１４を成している。端子群
１４の左右両側には、基板１１の両側位置設定用の略り
字形を成すトンボ１５ａ・１５ｂが設けられている。上
記端子群１４とトンボ１５ａ・工５ｂとの間には、約１
龍程度の余白部があり、この間に各３本づつダミー端子
１６ａ・・・、１６ｂ・・・が設けられている。尚、上
記ダミー端子１６ａ・・・、１６ｂ・・・の本数は、ダ
ミー端子を設けない場合には端子群１４の両端側にある
３本の半田メッキ膜厚が他の端子と比べ著しく厚くなる
という実験結果に基づいて決定されたものである。On a substrate 11 of a liquid crystal display element (LCD), a plurality of lines 12 are provided in the form of vertical stripes. A terminal forming portion 13 is formed at one end of the base vi11 so as to protrude over a predetermined length. On this terminal forming part 13,
The terminals 12a of each of the lines 12 are formed in parallel, thereby forming a terminal group 14. On both the left and right sides of the terminal group 14, register marks 15a and 15b forming an abbreviated letter shape for setting positions on both sides of the board 11 are provided. Approximately 1 inch
There is a margin about the size of a dragon, and three dummy terminals 16a, 16b, and so on are provided between these margins. In addition, regarding the number of the dummy terminals 16a..., 16b..., if no dummy terminals are provided, the thickness of the solder plating on the three terminals on both ends of the terminal group 14 will be significantly thicker than on the other terminals. This was determined based on the experimental results.
以上の構成を有する半田メッキ用基板１７において、前
記端子群１４を構成する各端子１２ａ・・・と、図示し
ないＦＰＣ（フレキシブル基板）の端子形成部に設けら
れた出力端子群との接続は、次のようにして行われる。In the solder plating board 17 having the above configuration, the terminals 12a constituting the terminal group 14 are connected to the output terminal group provided in the terminal forming part of an FPC (flexible board) not shown. This is done as follows.
先ず、パターンメッキ法により、前記基板１７の各端子
１．２ ａ・・・、ダミー端子１６ａ・・・、１６ｂ・
・・及びトンボ１５ａ・１５ｂ上に半田メッキし、フュ
ージング工程により、膜厚１３μｍの半田メッキ層を形
成する。次に、基板１７の端子形成部１３上に、前記Ｆ
ＰＣの端子形成部を対向して重ね合わせ、熱圧着工程に
より、各端子１２ａ・・・等とそれらに対応する前記Ｆ
ｐｃの出力端子等とを、半田メッキ膜を介して接続し、
これによりＬＣＤユニットが作製される。First, each terminal 1.2a..., dummy terminal 16a..., 16b... of the board 17 is formed by a pattern plating method.
...and the register marks 15a and 15b are plated with solder, and a solder plating layer with a thickness of 13 μm is formed by a fusing process. Next, the F
The terminal forming portions of the PCs are stacked facing each other, and through a thermocompression bonding process, each terminal 12a, etc. and the corresponding F
Connect the output terminals of the PC, etc. via the solder plating film,
In this way, an LCD unit is manufactured.
このようにして作製されたＬＣＤユニットは、前記した
パターンメッキ法によって、電流密度が増大する箇所で
膜厚が大きくなる影響はダミー端子１６ａ・・・、１６
ｂ・・・に生じ、他の各端子１２ａ・・・には及ばない
。その結果、各端子１２ａ・・・上に形成される半田メ
ッキ膜厚は、半田メッキ時において±１μｍの公差の精
度で均一にすることが可能となり、更にフュージング工
程による公差を含めても１３１２μｍの範囲におさめる
ことが可能となった。The LCD unit manufactured in this way is manufactured using the pattern plating method described above.
b..., and does not extend to the other terminals 12a.... As a result, the thickness of the solder plating film formed on each terminal 12a can be made uniform with a tolerance of ±1 μm during solder plating, and even including the tolerance due to the fusing process, it is 1312 μm thick. It was possible to keep it within range.
〔実施例２〕
本発明の第２実施例を第２図に基づいて説明する。基板
１１の端子形成部１３上には、中央部に基板１１の中央
位置設定用の略Ｕ字形を成すトンボ１５Ｃが設けられ、
このトンボ１５Ｃの左右両側には、複数の端子１２ａ・
・・から成る端子群１４・１４が形成されている。更に
、この端子群１４・１４の横力には、各３本のダミー端
子１６ａ・・・、１６ｂ・・・が設けられ、その外側に
は、基板１１の両側位置設定用の略り字形を成すトンボ
１５ａ・１５ｂが設けられている。これらトンボ１５ａ
・１５ｂと、端子形成部１３の両端との間の各余白部に
は、各々２本のダミー端子１６ｄ−１６ｄ、１６ｅ・１
６ｅが形成されると共に、中央位置設定用の前記トンボ
１５Ｃの中央余白部にも、２本のダミー端子１６Ｃ・１
６Ｃが設けられている。その他の構成は前記第１実施例
と同様であり、同一の機能を有する部材には同じ符号を
付記しである。[Embodiment 2] A second embodiment of the present invention will be described based on FIG. 2. On the terminal forming portion 13 of the board 11, a substantially U-shaped registration mark 15C for setting the center position of the board 11 is provided at the center.
There are a plurality of terminals 12a on both the left and right sides of this dragonfly 15C.
A terminal group 14 consisting of... is formed. Furthermore, three dummy terminals 16a..., 16b... are provided for the lateral force of the terminal groups 14, 14, and on the outside thereof, an abbreviated shape for setting the positions on both sides of the board 11 is provided. Register marks 15a and 15b are provided. These dragonflies 15a
- Two dummy terminals 16d-16d, 16e and 1 are provided in each margin between 15b and both ends of the terminal forming part 13.
6e is formed, and two dummy terminals 16C and 1 are also formed in the center margin of the registration mark 15C for setting the center position.
6C is provided. The rest of the structure is the same as that of the first embodiment, and members having the same functions are denoted by the same reference numerals.
本実施例では、第１実施例と同じ位置に設けられるダミ
ー端子１６ａ・・・、１６ｂ・・・によって、第１実施
例と同様に各端子１２ａ・・・上の半田メッキ膜厚を均
一化し得る。更に、他の余白部に設けた各ダミー端子１
６ｃ・１６ｄ・Ｌ６ｅによって一１上記均一化を促進し
得ると共に、上記各ダミー端子と、それに対応するＦＰ
Ｃ（フレキシブル基板）におけるダミー端子との接合に
よって、側基板における端子形成部間の接合強度が高め
られる。In this embodiment, the dummy terminals 16a, 16b, etc. provided at the same positions as in the first embodiment make the thickness of the solder plating film on each terminal 12a uniform, as in the first embodiment. obtain. Furthermore, each dummy terminal 1 provided in the other blank area
6c, 16d, and L6e can promote the above-mentioned uniformity, and each of the above-mentioned dummy terminals and the corresponding FP
The bonding strength between the terminal forming portions on the side substrate is increased by bonding with the dummy terminal on the flexible substrate C (flexible substrate).
本発明に係る半田メッキ用基板は、以上のように、端子
群及び基板の位置設定用のトンボが形成されている端子
形成部上の余白部のうち、少なくとも上記端子群と、基
板の両側位置設定用のトンボとの間の余白部にダミー端
子を設けた構成であるから、下記の効果を奏する。As described above, in the solder plating board according to the present invention, at least the terminal group and the positions on both sides of the board are located in the blank area on the terminal forming part where the register marks for setting the position of the terminal group and the board are formed. Since the dummy terminal is provided in the margin between the setting register mark, the following effects are achieved.
（１） 各端子上に均一な膜厚の半田メッキ層を形成し
得る。これによって、上記端子と、他の装置の対応端子
間とを接続する際、隣り合う端子間に半田のブリッジが
発生するのを抑制され、上記端子間のリークの発生を防
止し得る。(1) A solder plating layer of uniform thickness can be formed on each terminal. As a result, when the terminal is connected to the corresponding terminal of another device, the occurrence of solder bridges between adjacent terminals can be suppressed, and leakage between the terminals can be prevented.
（２） 端子形成部上の余白部分に設けられたダミー端
子は、端子形成部の補強機能を有し、対応するダミー端
子間の接合によって、対応端子形成部間の密着性が増大
する。これによって、接続端子間の接続安定性は向上す
る。(2) The dummy terminals provided in the margins above the terminal forming portions have a reinforcing function for the terminal forming portions, and the bonding between the corresponding dummy terminals increases the adhesion between the corresponding terminal forming portions. This improves the connection stability between the connection terminals.
（３） 半田接続の際、両端位置設定用のトンボから端
子群側への半田流出が、上記ダミー端子によって阻止さ
れるので、隣り合う端子間にわたる半田のブリッジの発
生を抑制し得る。(3) During solder connection, the dummy terminals prevent the solder from flowing out from the register marks for setting the positions of both ends to the terminal group side, so it is possible to suppress the occurrence of solder bridges between adjacent terminals.
（４） 上記（１）乃至（３）の効果により、液晶表表
示素子（ＬＣＤ）等のユニットの信頼性を高めることが
できる。(4) The effects of (1) to (3) above can improve the reliability of units such as liquid crystal display elements (LCDs).
第１図は本発明の一実施例を示す要部平面図、第２図は
本発明の他の実施例を示す要部平面図、第３図（ａ）は
パターンメッキ法における電流集中状態を示す従来例の
説明図、同図（ｂ）はその基板の拡大説明図である。
１１は基板、１２ａは端子、１３は端子形成部、１４は
端子群、１５ａ 〜１５ｃはトンボ、１６ａ〜１６ｅは
ダミー端子である。
ｓ １２Fig. 1 is a plan view of the main part showing one embodiment of the present invention, Fig. 2 is a plan view of the main part showing another embodiment of the invention, and Fig. 3 (a) shows the current concentration state in the pattern plating method. FIG. 1B is an enlarged explanatory view of the substrate of the conventional example shown in FIG. 11 is a substrate, 12a is a terminal, 13 is a terminal forming part, 14 is a terminal group, 15a to 15c are dragon marks, and 16a to 16e are dummy terminals. s 12
Claims (1)
いる端子形成部上の余白部のうら、少なくとも上記端子
群と、基板の両側位置設定用のトンボとの間の余白部に
ダミー端子を設けたことを特徴とする半田メッキ用基板
。 ２、上記ダミー端子は、上記の余白部に各々３本づつ設
けられている特許請求の範囲第１項記載の半田メッキ用
基板。[Claims] 1. The back of the margin on the terminal forming part where register marks for positioning the terminal group and the board are formed, at least between the terminal group and the register marks for positioning both sides of the board. A solder plating board characterized by having dummy terminals provided in the blank space. 2. The solder plating board according to claim 1, wherein three dummy terminals are provided in each of the blank spaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23391285A JPS6292989A (en) | 1985-10-18 | 1985-10-18 | Solder plating substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23391285A JPS6292989A (en) | 1985-10-18 | 1985-10-18 | Solder plating substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6292989A true JPS6292989A (en) | 1987-04-28 |
Family
ID=16962534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23391285A Pending JPS6292989A (en) | 1985-10-18 | 1985-10-18 | Solder plating substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6292989A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01252931A (en) * | 1988-04-01 | 1989-10-09 | Hitachi Ltd | Film substrate for liquid crystal display element |
| JP2004519009A (en) * | 2001-02-03 | 2004-06-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for improving the conductivity of transparent conductor lines |
| JP2006126087A (en) * | 2004-10-29 | 2006-05-18 | Nidec Sankyo Corp | Magnetoresistive element |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59116723A (en) * | 1982-12-24 | 1984-07-05 | Hitachi Ltd | Liquid-crystal display element |
| JPS6134771B2 (en) * | 1980-02-04 | 1986-08-09 | Iseki Agricult Mach |
-
1985
- 1985-10-18 JP JP23391285A patent/JPS6292989A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6134771B2 (en) * | 1980-02-04 | 1986-08-09 | Iseki Agricult Mach | |
| JPS59116723A (en) * | 1982-12-24 | 1984-07-05 | Hitachi Ltd | Liquid-crystal display element |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01252931A (en) * | 1988-04-01 | 1989-10-09 | Hitachi Ltd | Film substrate for liquid crystal display element |
| JP2004519009A (en) * | 2001-02-03 | 2004-06-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for improving the conductivity of transparent conductor lines |
| JP2006126087A (en) * | 2004-10-29 | 2006-05-18 | Nidec Sankyo Corp | Magnetoresistive element |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS60149079A (en) | Connector for display body unit | |
| JP3633566B2 (en) | Electronic device, manufacturing method thereof, and electronic apparatus | |
| US6744638B2 (en) | Construction and method for interconnecting flexible printed circuit and wiring board, liquid crystal display device, and method for manufacturing the same | |
| US5912654A (en) | Electric-circuit board for a display apparatus | |
| EP0491336A2 (en) | Electric circuit | |
| JPS6292989A (en) | Solder plating substrate | |
| JP2002329941A (en) | Connection structure of wiring board and connection structure of liquid crystal display panel | |
| JP3067038B2 (en) | Connection terminal arrangement structure of electronic components, tape carrier package, and liquid crystal display device using the tape carrier package | |
| JPS63213301A (en) | Printed wiring board with printed resistor | |
| JP2001109391A (en) | Substrate for connection and method for packaging plane display device using the substrate for connection | |
| JPH03126290A (en) | Printed wiring board | |
| JP3269128B2 (en) | Liquid crystal display device, electronic printing device, and semiconductor element mounting method | |
| JPH0828395B2 (en) | Flexible circuit board and liquid crystal display device | |
| JP2003131584A (en) | Liquid crystal display panel and its manufacturing method, liquid crystal display unit, and electronic equipment | |
| JPH1093210A (en) | Flexible circuit board and liquid crystal display unit | |
| JP2816281B2 (en) | Liquid crystal display | |
| JPH04106528A (en) | Liquid crystal display device | |
| JPS63299065A (en) | Connecting method for electronic component | |
| JPH10301138A (en) | Liquid crystal display device | |
| JP2503311B2 (en) | How to connect thermo-compression type film connector | |
| KR0170428B1 (en) | Connection structure of display panel | |
| JPS6211290A (en) | Circuit part mounting construction | |
| JPS6168871A (en) | Flexible printed circuit board | |
| JPS6097325A (en) | Display device | |
| JPH0579540U (en) | Display device |