JPS6292617A - Frequency control system - Google Patents

Abstract

PURPOSE:To improve the control by detecting a phase difference between a reference input and an output of a voltage controlled oscillator (or its frequency division output) at a prescribed tie, generating an output having a pulse width corresponding to the phase difference, obtaining a difference between a preceding output and a succeeding output and integrating the difference in a capacitor so as to narrow the loop gain band sufficiently. CONSTITUTION:When a voltage controlled oscillator 1 oscillates a specified frequency and the local clock frequency is coincident with the reference clock frequency, input pulses at both terminals I1, I2 of a charge pump 8 are opposite in polarity but same in the pulse width, then a mean value of an output current from a terminal O is '0' and a terminal voltage of a capacitor 9 is kept to the central value of a control voltage from the voltage controlled oscillator 1 when the frequency of the local clock is lowered, the input pulse width at the terminal I2 is longer than the pulse width at the terminal I1, the mean value of the output current from the terminal O is negative and the terminal voltage at the capacitor 9 is lowered. The oscillating frequency of the voltage controlled oscillator 1 rises and the input pulse width at the terminal I2 is decreased and the local clock frequency is restored to a frequency equal to that of the reference clock.

Description

[Detailed Description of the Invention] [Summary] In the frequency control loop, the first phase comparison means generates an output with a pulse width according to the phase difference of the voltage controlled oscillator output (or its frequency divided output) with respect to the reference input, The second phase detection means generates an output with a pulse width corresponding to the phase difference between the two signals after a certain period of time after the phase detection by the first phase comparison means, and the charge pump circuit generates an output with a pulse width corresponding to the phase difference between the two signals. Outputs of equal amplitude and opposite polarity of pulse widths corresponding to the outputs of the phase comparison means 2 are generated and integrated into a capacitor, and the oscillation frequency of the voltage controlled oscillator is controlled by the terminal voltage of this capacitor. , control using a signal proportional to the frequency difference between both inputs, that is, frequency control, can be performed, the loop gain band can be narrowed, and frequency changes of less than one clock can be handled.

[Industrial application field]

The present invention relates to a frequency control loop, and more particularly to a frequency control method for controlling the oscillation frequency of a voltage controlled oscillator by detecting the amount of phase change per unit time between an output and a reference input.

In the frequency control loop, the voltage controlled oscillator output is compared with the reference input and the resulting error signal voltage is used to control the voltage controlled oscillator to achieve frequency synchronization with respect to the reference input. It is desired that the frequency can be narrowed, and that even if the frequency comparison signal changes in frequency within one clock, it can be detected and controlled.

[Conventional technology]

As a frequency synchronization method in a frequency control loop, a phase synchronization method (PLL method) and a frequency synchronization method using pulse counting are known.

The phase synchronization method has a phase comparator and controls the voltage controlled oscillator using the error signal voltage obtained by comparing all phases with the voltage controlled oscillator output and the reference clock input, and synchronizes the frequency with the reference clock. be.

In addition, the frequency synchronization method using pulse counting compares the voltage-controlled oscillator output and the reference clock input, counts the frequency difference using a counter, and converts this counter output into a digital signal.
This voltage is converted into a control signal voltage by an analog (D-A) converter, and the voltage controlled oscillator is controlled and frequency synchronized using this voltage.

[Problem that the invention seeks to solve]

In the phase locking method, the loop gain band is approximately determined by the phase comparator, comparison frequency, and conversion gain of the voltage controlled oscillator. Although it is possible to narrow this band by inserting a loop filter, it is not possible to change it significantly. The problem is that it cannot be done.

In addition, in the frequency synchronization method using pulse counting, not only is the configuration complicated and the circuit scale becomes large, but also the output value of the frequency comparison counter does not change for frequency changes of one pulse or less, making frequency control difficult. The problem is that it cannot be done.

[Means for solving problems]

In order to solve the above problems, the system of the present invention has a basic configuration as shown in FIG.

101 is a voltage controlled oscillator whose oscillation frequency is controlled by the terminal voltage of a capacitor 105.

Reference numeral 102 denotes a first phase comparison means that detects the phase difference between the reference input and the output of the voltage controlled oscillator (or its frequency-divided output), and generates a pulse width corresponding to the phase difference.

Reference numeral 103 denotes a second phase comparison means, which detects the phase difference between the reference input and the voltage controlled oscillator output ('! Takeno's frequency division output) after a certain period of time after the first phase comparison means detects the phase difference. The pulse width is generated accordingly.

Reference numeral 104 is a charge pump circuit, in which the output of the first phase comparison means (102) is connected to the first input, and the output of the second phase comparison means (103) is connected to the second input with opposite polarity. The pulse widths corresponding to both the input and output sides are opposite in polarity to each other and the output widths are generated.

105 is a capacitor, which is a charge pump circuit (10
4) Integrate the output.

[Effect]

In the method of the present invention, the phase difference between the reference input and the voltage-controlled oscillator output (or its divided output) is detected at certain intervals, and an output with a pulse width corresponding to the phase difference is generated. By calculating the difference between Since the control is performed, the loop gain band can be sufficiently narrowed, and control can be performed even if the frequency difference between the reference input and the output of the voltage controlled oscillator (or its frequency-divided output) is within one clock.

〔Example〕

FIG. 2 shows an embodiment of the system of the present invention. 1
is a voltage controlled oscillator (VCXO), for example 16.
Generates a 384 MHz sine wave oscillation output. A counter 2 counts the output cycles of the voltage controlled oscillator 1 and divides the frequency into, for example, 1/256 to generate a local tarlock of 64 kHz. 3 and 4 are clip-flops at J-, respectively, and the logic level '1' is applied to the J input and the input.
By adding a reference clock of 64 KHz and a local clock to the clock CLK, a rectangular wave signal Ql whose frequency is divided by two is output.
Qz produces its inverted signal at outputs Qx and Qg.

5.6 is an AND gate, and each signal Q! and Q
z, generates an output of the AND of Qx and Qx. The output pulse width of the AND gate 5 is equal to the phase difference between the reference clock and the local clock. Further, the output pulse width of the AND gate 6 is also equal to the phase difference between the reference clock and the local clock. The output of the AND gate 6 passes through a circuit consisting of a transistor 7 and produces an inverted output on its collector side.

8 is a three-state charge pump circuit;
The input terminal It has two input terminals Is and Ig and an output terminal 0.

■! When an input pulse of opposite polarity is applied to both inputs, an output pulse of opposite polarity with the same pulse width and equal amplitude is generated at output terminal 0. A capacitor 9 serves as an analog memory, and integrates the output of the charge pump circuit 8 to generate a DC output voltage.

This signal is given to the voltage controlled oscillator 1 as a control voltage.

FIG. 3 shows the valley signals in the nine embodiments shown in FIG. 2, where (a) is the reference clock and (b) is the J
-The Q1 output of flip 7a Tsubu 3, (e) is the same <
Ql output, (d) local clock, (e) J-
Q-deba of flip-flop 4, (f) is also i2
Tagata, (g) output of AND gate 5, (h) is AND
The output of gate 6, (i) is the collector output of transistor 7, which are also indicated by the same reference numerals at corresponding positions in FIG.

Now, when the voltage controlled oscillator 1 oscillates at the specified frequency and the local clock frequency matches the reference clock frequency, the input pulses at both terminals Ix and ItO of the charge pump 8 have opposite polarities and the same pulse width. Therefore, the average value of the output current from the terminal 0 is 0, and the terminal voltage of the capacitor 9 is maintained at the center value of the voltage controlled oscillator 10 control voltage.

When the frequency of the local tarlock decreases for some reason, the input pulse width at terminal I2 becomes longer than the pulse width at terminal It, so the average value of the output current from terminal O becomes negative, and the terminal voltage of capacitor 9 decreases. do. The oscillation frequency of the voltage controlled oscillator 1 increases due to the decrease in the control voltage, thereby the input pulse width of the terminal 2 decreases, and the local clock frequency is pulled back to the same frequency as the reference clock.

Also, when the local tarlock frequency increases, the input pulse width of terminal I2 becomes shorter than the pulse width of terminal ■1, the average value of the output current from terminal 0 becomes positive, and the terminal voltage of capacitor 9 increases. do. As a result, the oscillation frequency of the voltage controlled oscillator 1 is lowered, and the local clock frequency is pulled back to the same frequency as the reference clock.

In this way, in the method of the present invention, a voltage (or current) proportional to the phase difference at time t2 between the local clock and the reference clock is charged from a voltage ('! current) proportional to the phase difference at time t1. By subtracting using a pump circuit and an analog memory consisting of a capacitor, a voltage (or current) proportional to the amount of phase change per unit time (titt), that is, a frequency difference, is obtained, and by this voltage (or current), Controls the oscillation frequency of the voltage controlled oscillator. In other words, in the method of the present invention, frequency control is performed.

In conventional phase control systems, the voltage controlled oscillator becomes a differential element within the loop, so if there is an integral element such as a capacitor in the rube circle, the system may oscillate and become unstable. .

However, in the case of frequency control, the voltage controlled oscillator only converts the control voltage and the oscillation frequency and does not serve as a differential element. The configuration of the present invention only includes a capacitor as an integral element in the loop, so there is no restriction on narrowing the loop gain band, and it is possible to sufficiently slow down the response and improve operational stability. It is possible to improve control accuracy while maintaining

Furthermore, as is clear from the above explanation, in the method of the present invention,
Even if the frequency difference between the local clock and the reference clock is within 1 clock, a control voltage corresponding to the difference can be obtained, and therefore frequency control can be performed continuously at 1 where the frequency difference is close to 0.

Note that the local tally for phase comparison with the reference clock is 1! It goes without saying that it is also possible to use the output of the control oscillator instead of the divided output.

〔Effect of the invention〕

As explained above, according to the method of the present invention, frequency control is performed in the frequency control loop by controlling the voltage SII:j by a signal proportional to the amount of phase change per unit time, that is, the frequency difference. Loop gain band w? It can be made sufficiently narrow, and control accuracy can be improved while maintaining operational stability. Furthermore, in the uninvented method, even if the frequency difference between the local clock whose phase is compared and the reference clock is within one clock, a control voltage corresponding to the difference can be obtained and frequency control can be performed continuously.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a time chart showing various signals in FIG. 2. 1... Voltage controlled oscillator (VCXO) 2... Counter 3.4... Flip-flop in J- 5.6... AND gate 7 Transistor 8... Three-state charge pump circuit 9...
capacitor

Claims (1)

[Claims] First phase comparison means that compares the phases of the reference input and the voltage-controlled oscillator (101) output (or its frequency-divided output) and generates an output with a pulse width corresponding to the phase difference between the two signals. (102)
After a certain period of time after the first phase comparison means (102) detects the phase difference, the reference input and the output of the voltage controlled oscillator (101) (or its divided output) are compared in phase, and the phase difference between the two signals is determined. second phase comparator means (10
3), the output of the first phase comparison means (102) is applied to the first input, the output of the second phase comparison means (103) is applied to the second input with opposite polarity, and both the outputs are applied. A three-state charge pump circuit (104) that generates outputs of equal amplitude and opposite polarity with pulse widths corresponding to the input; and a capacitor (105) that integrates the output of the charge pump circuit (104); A frequency control method characterized in that the oscillation frequency of a voltage controlled oscillation circuit (101) is controlled by the terminal voltage of a capacitor (105).