JPS6292539A - Data transmission method - Google Patents

Abstract

PURPOSE:To simplify the system constitution by sending a data during a positive half cycle of a power supply and inverting the data at the suceeding negative half period and sending the result so as to detect the sent data error easily. CONSTITUTION:A tail end car In is connected to the back side of a head car I1 via intermediate cars I2-In-1 and a front/back switch 5 is provided to the head car I1 and the tail end car In. A display device 6 and a setting device 7 are connected to each switch device 5, a signal from the switch 5 is received to apply display and setting required for devices placed in a driver room or a conductor room. Further, a converter 8 provided to the head car I1, intermediate cars I2-In-1 and the tail end car In sends a state signal of each car to a connection line. In the transmission of the data, one bit of data is send during the period when a positive signal of the power supply is applied, a complement data to the data transferred just before the power supply is transferred to the negative signal and the error detection of the sent data is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission method for transmitting data under conditions where a high level of noise occurs, such as in a railway vehicle.

[Conventional technology]

Generally, in a railway vehicle, the status of each car number is transmitted to the lead car where the driver is located and the tail car where the conductor is located to monitor whether the doors, brakes, etc. are operating normally. For this reason, conventionally, signals representing each state were transmitted from each car number to the leading vehicle and the trailing vehicle. In this case, among railway vehicles, especially electric trains, data is transmitted in an environment where high-level electrical noise occurs, so a parity check is used as a means to prevent errors.

[Problem that the invention seeks to solve]

However, error detection using a parity check not only requires a complicated configuration, but also has the drawback that an even number of errors cannot be detected.

[Means for solving problems]

In order to solve these drawbacks, the present invention is configured such that the phase of data transmitted in the positive half cycle of the power supply is inverted in the next negative half cycle before being transmitted.

[Effect]

Erroneous errors can be checked by comparing the data sent in the positive half cycle with the data sent in the negative half cycle.

〔Example〕

FIG. 2 is a diagram showing the train configuration, and shows one train formation. In the figure, 11 is a leading vehicle, 12 to 1n-1 are intermediate vehicles, and 1n is a trailing vehicle. The leading vehicle 11 and the trailing vehicle 1n are provided with a front/rear switch 5, a display 6, a setting device 7, and a converter 8, and the intermediate vehicles 12 to 1n-1 are provided with a converter 8.
only is provided.

FIG. 3 shows a state in which vehicles in such a formation are connected to form three formations.

The display device 6 and the setting device T receive signals from the front/rear changeover device 5 and can perform necessary displays and settings as equipment placed in the driver's cab or conductor's room. converter 8
is designed to generate a signal that sends the status of each car number to the connecting line.

An example of transmitting a signal consisting of address A1 information as shown in FIG. 4 in a device configured in this way will be described. Note that FIG. 4(a) is a diagram with the topmost pit on the left side, and FIG. 4(b) is a diagram with the topmost pit on the right side, and the contents are the same. Address A is assumed to be composed of 5-digit pits with AO as the lowest pit and A4 as the highest pit, and information is composed of 8 bits with DO as the lowest pit and DI as the highest pit. Then, the address data is roololJ and the information data is rololo
An example of oollJ will be explained.

Each device is commonly supplied with a power source having a frequency of 500 Hz as shown in FIG. 1(a), and the waveform of this power source is used as it is as a clock signal for each device. Then, in synchronization with this power supply waveform, as shown in Figure 1 (
As shown in b), start signal St+address signal S
The data signal Sd and the stop signal Sp are transmitted sequentially, and the answer back signal sb is transmitted at the end if necessary. Among the signals, the address signal Ss and the information signal Sd are Every time a positive side signal is supplied, each pit of address data A and information data D is sent out in sequence, and every time a negative side signal of the power supply is supplied, data that is the complement of the data sent out in the previous positive side signal is sent out. It is supposed to be done. Furthermore, data is transmitted sequentially from the lowest pit to the highest pit.

As mentioned above, the address data is r 00101 J, so if the lowest pit is AO1 and the highest pit is A4, the address data is AO=1, AI=0, A
2=1. A3=O, A4=0. For this reason,
As shown in Figure 1(b), this data changes from the lowest pitch (AO) to the highest pitch (PI)A every time the positive side signal of the power supply is supplied.
It is sent out sequentially in four directions.

Similarly, since the information data is r 00100011 J, the information signal Sd is transmitted from the lowest bit (rDoJ) to the highest pit "DI" every time the positive side signal of the power supply is supplied. Then, each time the negative side signal of the power supply is supplied, the complement data of the data sent out in the immediately preceding positive side signal is sent out. For example, since AO=“1”, the complement π, that is, the “0” level signal is transmitted in synchronization with the negative side signal of the next power supply. Also, Denita A2-A4, D.

As for ~D7, signals are similarly transmitted in synchronization with the negative side signal of the power supply immediately after.

In the signal transmitted in this manner, the information of the same pit is sent twice, and complement data is sent in which the data state is different between the first state and the subsequent state, so that the error detection accuracy is improved. In other words, A is synchronized with the positive side signal of the power supply.
O, AI, A2. A3.

A4 address signal and Do, DI, D2 . D3
.

D4. D5. D6. The data signal of DI is transmitted, and in synchronization with the negative side signal of the power supply, AO, AI, A2 . A3. A4 and DO, DI, D2, D3, D4,
Since D5, D6, and DI signals are transmitted, check ■~ correction against AO~A4, and DO~D7
Error detection can be easily performed by applying the DO~ correction to the above. In other words, unlike a parity check, unless an error occurs when transmitting a signal synchronized with the positive side signal of the power supply waveform, and an error occurs immediately after that when transmitting a signal synchronized with the negative side signal, Can be detected accurately.

As mentioned above, since the positive side signal and the negative side signal of the power supply are synchronized and transmitted while the negative side is inverted while the positive side signal is transmitted, as shown in Figure 1 (b), the transmission In the data that should be
Even if there are consecutive “0” levels or consecutive “1” levels,
No matter how the "0" level and the rlJ level are combined, the address signal Sa and information signal Sd may remain in the same state continuously for up to 2 bits, but the same state cannot occur continuously for 3 or more bits. do not have.

Therefore, if a series of identical states on 3 bits are generated in a consequential manner, it can be easily determined that the state is not the address signal 81 or the information signal Sd. Therefore, in the present invention, as shown in FIG. 1(b), a signal of three or more consecutive bits of "1" level is provided prior to the address signal S&, and this is used as the start signal St.
Following the information pit Sd, a state in which the OJ level continues for 3 bits is provided, and this is used as the stop signal Sp.

Therefore, if the signal sent after the start signal St is the address signal SIL, and the stop signal Sp is detected after the information signal SdO, the period of one frame can be known with certainty, and accurate frame synchronization can be achieved. .

The positive side signal of the power supply is f#! 7! 'It is desirable that the signal that is transmitted as the ipsilateral signal to the intervening side signal remains stable at the [1co or rOJ level] during the period that the signal is being transmitted, but this may not necessarily be the case depending on the condition of the transmission path. However, there is no guarantee that the transmission will be stable. Therefore, when a signal as shown in FIG. 5(1) is detected, depending on the timing of sampling this data, the "1" level and the "0" level may be detected at different times (υ), resulting in K. For this reason, Fig. 5 (b
), if the sampling is performed using pulses with a sufficiently short period compared to the duration of the signal T, and if the same state is detected at least twice, it will be determined that a normal signal has been detected. , stable judgment can be made. However, since the period T1 from the signal generation time t1 is in a transient state and is not stable, detection is performed after this period has passed.

In the example of FIG. 5, detection starts after time t3, and
At 6 and t7, the "1" level is detected twice in succession for the first time, and it is determined that this signal is at the "1" level.

〔Effect of the invention〕

As explained above, in this invention, the data transmitted during the positive half cycle of the power supply and the data transmitted during the subsequent negative half cycle are inverted and transmitted, so that the transmitted data may be erroneous. can be detected easily, and the detection is more stable than the parity check method.

[Brief explanation of drawings]

Figure 1 is a diagram showing how to transmit data to explain this invention, Figure 2 is a diagram showing one train formation, Figure 3 is a diagram showing three train formations, and Figure 4 is a diagram showing how to transmit data. FIG. 5 is a diagram showing address data and information data to be used, and FIG. 5 is a diagram showing a sampling state. 11...Lead car, 12~In-1...Intermediate car, 1n...Rear car, 5...-front/rear switch, 6・o
s: Display, T: Setting device, 8: Converter. Procedural amendment (voluntary) 1. Display of case 1985 Patent Application No. 231040 2, Name of invention data transmission method 3, Person making amendment Relationship with case Patent Applicant name (name)
Koito Kogyo Co., Ltd. 5, Column 6 of the detailed description of the invention in the specification to be amended, Contents of the amendment (1) "Ph" on page 2, line 2 of the specification is amended to read "door". (2) "Connection line" on page 3, line 14 of the same book is corrected to "through line." (3) “Data signal” on page 4, line 12 of the same book is “information signal”
and correct it. (4) "A2" on page 5, line 19 of the Ministry of Finance is corrected to "A1."that's all

Claims (1)

[Claims] In a data transmission method in which multiple devices operate on a common AC power source, each device uses that AC power source as a synchronous clock pulse, and transmits data in synchronization with the synchronous clock pulse, the positive side signal of the power source is supplied. Data transmission is characterized in that one pit of data is transmitted during the period when the power supply changes to a negative side signal, and when the power supply changes to a negative side signal, the complement data of the data transmitted at the time of the positive side signal of the power supply that was transmitted immediately before is transmitted. Method.