JPS6290462U - - Google Patents

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Publication number
JPS6290462U
JPS6290462U JP18182785U JP18182785U JPS6290462U JP S6290462 U JPS6290462 U JP S6290462U JP 18182785 U JP18182785 U JP 18182785U JP 18182785 U JP18182785 U JP 18182785U JP S6290462 U JPS6290462 U JP S6290462U
Authority
JP
Japan
Prior art keywords
lpf
conversion
sample
digital recording
hold circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18182785U
Other languages
Japanese (ja)
Other versions
JPH0548295Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985181827U priority Critical patent/JPH0548295Y2/ja
Publication of JPS6290462U publication Critical patent/JPS6290462U/ja
Application granted granted Critical
Publication of JPH0548295Y2 publication Critical patent/JPH0548295Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
である。第２図は、この考案の他の実施例を示す
ブロツク図である。第３図は、従来装置を示すブ
ロツク図である。 １９…Ａ／Ｄ変換、Ｄ／Ａ変換兼用ＬＰＦ、３
８…サンプルホールド、デイグリツチ兼用回路。 FIG. 1 is a block diagram showing one embodiment of this invention. FIG. 2 is a block diagram showing another embodiment of this invention. FIG. 3 is a block diagram showing a conventional device. 19...A/D conversion, D/A conversion combined LPF, 3
8...Sample hold and day glitch circuit.

Claims (1)

【実用新案登録請求の範囲】 １ Ａ／Ｄ変換用ＬＰＦとＤ／Ａ変換用ＬＰＦと
を兼用したことを特徴とするデイジタル形記録再
生装置。 ２ 前記兼用されたＬＰＦの前後に配されるデイ
グリツチ回路とＡ／Ｄ変換用サンプルホールド回
路とを兼用したことを特徴とする実用新案登録請
求の範囲第１項に記載のデイジタル形記録再生装
置。[Claims for Utility Model Registration] 1. A digital recording/reproducing device characterized by serving as both an A/D conversion LPF and a D/A conversion LPF. 2. The digital recording and reproducing apparatus according to claim 1, wherein the day-glitch circuit and the A/D conversion sample-hold circuit, which are arranged before and after the dual-purpose LPF, also serve as a sample-and-hold circuit.
JP1985181827U 1985-11-26 1985-11-26 Expired - Lifetime JPH0548295Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985181827U JPH0548295Y2 (en) 1985-11-26 1985-11-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985181827U JPH0548295Y2 (en) 1985-11-26 1985-11-26

Publications (2)

Publication Number Publication Date
JPS6290462U true JPS6290462U (en) 1987-06-10
JPH0548295Y2 JPH0548295Y2 (en) 1993-12-22

Family

ID=31127055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985181827U Expired - Lifetime JPH0548295Y2 (en) 1985-11-26 1985-11-26

Country Status (1)

Country Link
JP (1) JPH0548295Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55157117A (en) * 1979-05-25 1980-12-06 Matsushita Electric Ind Co Ltd Pcm recording and reproducing device
JPS58141417U (en) * 1982-03-18 1983-09-22 ソニー株式会社 Recording/playback device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55157117A (en) * 1979-05-25 1980-12-06 Matsushita Electric Ind Co Ltd Pcm recording and reproducing device
JPS58141417U (en) * 1982-03-18 1983-09-22 ソニー株式会社 Recording/playback device

Also Published As

Publication number Publication date
JPH0548295Y2 (en) 1993-12-22

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