JPS628815B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a so-called pipeline arithmetic unit.

Various methods have been proposed to speed up computer processing. The present invention is one of those methods.
Let's talk about the pipeline arithmetic unit.
A pipeline arithmetic unit is one that processes data by continuously sending it to a plurality of arithmetic stages one after another. In this way, the pipeline arithmetic unit itself can perform data processing at a fairly high speed.

However, although the pipeline arithmetic unit itself performs high-speed processing, the instruction units, memory, etc.
Because communication with the unit is not smooth,
In the end, the processing speed of the computer system as a whole has not reached the expected theoretical speed. Regarding this point, no sufficient solution has yet been discussed. This is because the pipeline arithmetic unit itself has not yet entered the stage of complete practical use.

Accordingly, an object of the present invention is to propose a method of controlling a pipeline computing unit that can substantially approach the expected theoretical computing speed.

In accordance with the above object, the present invention provides a pipeline arithmetic unit that includes a plurality of serially connected arithmetic stages and sequentially processes data included in a plurality of elements for each instruction. The present invention is characterized in that a stage is provided for counting the number of elements of a plurality of elements, and when the count reaches a predetermined count value, a predetermined warning signal is supplied to the peripheral device.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a general pipeline arithmetic unit. In this figure, D2
and D3 mean data included in the first element group and the second element group, respectively, and these become input data. Each input data is once stored in the registers R2A and R3A of the A stage, and then reaches the registers R2B and R3B of the B stage via the corresponding preshifters PRS2 and PRS3. The preshifter (PRS) is used, for example, in floating point addition.
Operations such as comparing the exponent parts and matching the numerical value to the larger one are performed.

The data in registers R2B and R3B are added to adder ADD and sent to register R in C stage.
1C, is stored in the register RID of the D stage via the post-shifter PTS, and is then output as output data D1.

The process of the pipeline operation described above is clear from FIG. FIG. 2 is a time chart schematically showing the flow of elements running through the stage of FIG. These time charts are stacked in four stages (1 to 4 in the figure), and each stage corresponds to each of the stages A, B, C, and D described above. The numbers 1 to 9 in the diagram are element numbers that are processed consecutively (the contents are the data described above)
It shows. As shown in FIG.
A and R3A are at the same stage, and each data of elements 1, 2, 3, . . . 9 is stored sequentially as shown in column 1 of FIG. These elements 1,
When each data of 2, 3...9 moves to the next B stage (column 2 in Figure 2), the next new element is transferred to the same stage 1.
It comes in like a column. In the end, register (R2
A, R3A, R2B, R3B, R1C, R1D)
If we look at the elements that enter in the vertical direction in chronological order, they shift one element at a time. This shift is done in units of one cycle clock. As is clear from this figure, the pipeline arithmetic unit processes a series of data densely without gaps, and is therefore expected to perform extremely high-speed processing.

However, in reality, its high speed is not fully demonstrated. That is, since the peripheral devices connected to the pipeline arithmetic unit are not efficiently exchanged, the actual processing speed of the entire computer system is not so high. The peripheral devices referred to here mainly refer to instruction units. The instruction unit provides predetermined instructions to various devices within the computer system. For example, the instruction unit instructs a memory (not shown) to output (read) the input data D2 and D3 of FIG. 1 to the pipeline arithmetic unit. Alternatively, it instructs that the output data D1 from the pipeline arithmetic unit in FIG. 1 should be input (written) into a memory (not shown). The present invention refers to the former of the above-mentioned instructions, but in this case, instructing the memory to perform a read operation after inputting the input data D2 and D3 would result in wasted time. This poses a problem in increasing the processing speed described above.

Therefore, the present invention proposes a configuration as shown in FIG.
FIG. 3 is a block diagram showing an embodiment for implementing the control method of the present invention. However, the system on the right side of the figure is as already explained in FIG. Therefore, the system on the left side of the figure is introduced based on the present invention. What should be input to the system 30 is the number of elements EN (1, 2, 3, . . . 9 in FIG. 2, also called vector length) to be processed in one instruction. This number of elements EN is made clear when the instruction unit instructs the pipeline arithmetic unit. The number of elements EN is
Furthermore, a counting means, for example a counter (CNTA) 31
Preset to . At this time, the first corresponding data is stored in the A stage registers (R2A, R3A). Thereafter, the data is shifted downward in the figure one stage at a time in synchronization with the one cycle clock CC, and at the same time, the contents of the counter 31 are subtracted (down-counted) by 1 by the decrement means (-1) 32. Ru. Here, the input data D2 and D3 described above are read out from the memory several cycles in advance of the timing at which reading is to be started.
Since the gist of the present invention is to form a warning signal W in the instruction unit before the clock, the appearance of a predetermined element in one element group is first detected for this purpose. . That is, when the count value of the counter 31 reaches, for example, 4, an operation for advance notice is activated. The first step in this activation is to detect the count value 4 of the counter 31, and the circuit 33 that performs this is comprised of, for example, a decoder. The decoder 33 outputs logic "1" at the time of this detection. This logic "1" is the aforementioned warning signal. The stage at which this notice signal is sent is arbitrary, and the set value for the decoder of the count value may be set to 3 or 5 instead of the above-mentioned 4.

FIG. 4 explains the operation of the configuration shown in FIG.
This is a time chart for clarifying the method of the present invention. In addition, in order to speed up understanding, it is drawn to have a chronological relationship with the time chart in Figure 2. The count value 4 of the counter (CNTA) in column 5 in the figure is the count value 4 described above, and the decoder 33 thereby sends out a logic "1". This logic "1" becomes the notice signal W. T is the margin period that should be taken when giving advance notice.

The advance notice signal obtained in this way prepares for the input of data from the memory in the next instruction, since the input of data from the memory (elements 1, 2, 3...) in the relevant instruction is nearing the end. It has the meaning of "Let's do it." That is, the memory can stand by and be ready to supply data at any time upon receiving an instruction from the instruction unit. This is also the principle of high-speed processing brought about by the present invention.

FIG. 5 is a time chart showing one embodiment of the method of the present invention. In this figure, for example, instruction 1 with 6 elements and instruction 2 with 10 elements are shown. In instruction 1 with 6 elements, when the pipeline arithmetic unit reaches, for example, 4 remaining, the warning signal W The advance notice signal W activates the next command start (START(2)). In this way, a series of instructions will be executed closely without any gaps.

In the first place, if the number of elements is the same for all instructions, there is neither room nor necessity to introduce a control method such as the present invention. However, the number of elements varies for each instruction. For this purpose, by initializing the number of elements in a counter each time and subtracting it by 1 in synchronization with the cycle clock, no matter what vector length the instruction is, it will always be executed at a certain timing before inputting all data. A notice can be issued.

As explained above, according to the present invention, the cooperation between the pipeline arithmetic unit and the peripheral devices that interact with it is
The processing speed of the entire computer system is greatly improved because the processing is performed continuously without any wasted time.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of the configuration of a general pipeline arithmetic unit, Fig. 2 is a time chart schematically showing the flow of elements running through the stages shown in Fig. 1, and Fig. 3 is a control diagram of the present invention. FIG. 4 is a block diagram showing an example of implementing the method; FIG. 4 is a time chart for explaining the operation of the configuration shown in FIG. 3 and clarifying the method of the present invention; FIG. 3 is a time chart showing an example of an embodiment when the method is executed. In the figure, 30 is a system introduced by the present invention,
31 is a counter, 32 is a decrement means, 33
is a decoder, and W is a warning signal.

Claims (1)

[Claims] 1. A pipeline arithmetic unit that consists of a plurality of serially connected arithmetic stages and processes each data of a group of elements while sequentially shifting it to the next arithmetic stage in synchronization with a cycle clock. , a computer system comprising a peripheral device linked to the pipeline arithmetic unit, a system that operates in the same step as the pipeline arithmetic unit is provided in parallel with the pipeline arithmetic unit, and a first stage of the system is provided. is provided with counter means for presetting the number of elements in the group of elements, counts down the number of elements preset in the counter means in synchronization with the cycle clock, and by the down count, the number of elements in the group of elements is preset. Detecting the appearance of the stage a predetermined number of cycle clocks before the arrival of the last element of the elements, forming a warning signal at the timing of the detection and sending it to the peripheral device,
1. A method for controlling a pipeline computing unit, characterized in that the peripheral device is prompted to prepare for execution of a predetermined process.