JPS628766U

JPS628766U -

Info

Publication number: JPS628766U
Application number: JP9751485U
Authority: JP
Priority date: 1985-06-28
Filing date: 1985-06-28
Publication date: 1987-01-20

Description

[Brief explanation of the drawing]

第１図は本考案の実施例の基本構成を示すブロ
ツク図、第２図は本考案に係る固定遅延線による
ＤＣ固定処理を説明するブロツク図と波形図、第
３図は第１図のレベルスライス回路の動作を説明
する波形図、第４図および第５図はそれぞれ本考
案の実施例の全体構成を示すブロツク図、第６図
はＣＣＤの出力信号の波形を示す波形図、第７図
は従来の分離形カメラの構成例を示すブロツク図
、第８図は従来のサンプルホールドによる信号再
生を示す波形図、第９図Ａ，Ｂは従来の分離形カ
メラにおけるアースインピーダンスの構成を示す
ブロツク図、第１０図はＣＣＤ信号出力のノイズ
を示す波形図である。１……カメラヘツド、３……ＣＣＤ、５……ケ
ーブル、２１……ＤＣ固定回路、２１Ａ……クラ
ンプ回路、２２……レベルスライス回路、２３…
…ローパスフイルタ、２４……プロセス回路、２
５……同期発生回路、２６……クランプパルス発
生回路、３１……固定遅延線、３２……減算器。 FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention, FIG. 2 is a block diagram and waveform diagram illustrating DC fixing processing by a fixed delay line according to the present invention, and FIG. 3 is a level diagram of FIG. 1. 4 and 5 are block diagrams showing the overall configuration of the embodiment of the present invention, respectively. FIG. 6 is a waveform diagram showing the waveform of the output signal of the CCD, and FIG. is a block diagram showing an example of the configuration of a conventional detachable camera, FIG. 8 is a waveform diagram showing signal reproduction by conventional sample and hold, and FIGS. 9A and B are blocks showing the configuration of earth impedance in a conventional detachable camera. 10 are waveform diagrams showing noise in the CCD signal output. 1... Camera head, 3... CCD, 5... Cable, 21... DC fixed circuit, 21A... Clamp circuit, 22... Level slice circuit, 23...
...Low pass filter, 24...Process circuit, 2
5...Synchronization generation circuit, 26...Clamp pulse generation circuit, 31...Fixed delay line, 32...Subtractor.

Claims

[Claims for Utility Model Registration] (1) a. In a head-separated solid-state imaging device in which an imaging section including a solid-state imaging device and a signal processing section are coupled via a signal cable, (b) the signal is transmitted from the imaging section to the signal processing section; (c) a DC fixed circuit that makes the reference level part constant for the image sensor output signal sent through the cable; (d) a level slicing circuit that slices the imaging signal side with a biased level to remove noise superimposed below a certain level; and (d) a low-pass circuit that uses the Nyquist frequency of the imaging signal as a cutoff frequency for the output signal of the level slicing circuit. A solid-state imaging device, comprising: a filter, and a captured video signal is extracted through the low-pass filter. (2) Utility Model Registration A solid-state imaging device according to claim 1, characterized in that the DC fixing circuit is a pulse clamp circuit that performs operation every horizontal scanning period of an image sensor output signal. (3) Utility model registration In the device according to claim 1, the DC fixed circuit is connected to a delay line for a feed-through period of the image sensor output signal, and the delayed signal by the delay line is subtracted from the original non-delayed signal. What is claimed is: 1. A solid-state imaging device comprising a subtracter.