JPS6286716A - Formation of ohmic contact between metal and semiconductor and apparatus for the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improved apparatus for forming ohmic connections between metals and semiconductors, particularly P- or N-doped silicon. and related methods.

(Prior Art) Many different techniques such as methods such as grown bonding, alloy bonding, planar technology, Planox (trade name of the Italian company Essedie Fuse Microelesoto Ichica Esse Pia) technology, etc. The manufacture of any integrated circuit, such as the manufacture of any semiconductor device manufactured by the It is necessary to form an ohmic connection between the metallic materials used to create the interconnect or to connect to the support on the "back" part of the same.

The metal materials used are different types of aluminum,
Tungsten, platinum, their alloys, nitrides and silicides, and heavily doped polycrystalline silicon are examples of suitable materials used commercially.

This type of connection formed between a material with metallic conduction and a semiconductor material must exhibit substantial linearity and symmetry with respect to the original current-voltage characteristics (ohmic connection), i.e. it , at least the origin of the axis (the
The origin of the axes) must not lead to current "rectification" phenomena or appreciable non-linearities in the characteristic part (maximum foreseeable strength of the operating current).

Furthermore, the connection resistance must be as low as possible for obvious reasons such as power consumption, switching times, etc.

In general, according to today's known methods, a new layer of photoresist is applied, after which the necessary diffusion has already been carried out and the surface insulating layer of oxide or an equivalent non-conducting compound has been modified, through which The method of forming such connections on the wafer, forming the necessary "windows" by known photolithographic techniques for masking, takes place under substantially anisotropic or in any case controlled conditions. ,semiconductor(
Typically an oxide (e.g. doped silicon) corresponding to a window formed in the photoresist layer is exposed until the oxide (e.g. doped silicon) is exposed.
It is contemplated to remove the non-conducting material layer, for example Sing, to ensure that the size of the section on which the ohmic connection is formed is well defined.

Therefore, some of the ions are accelerated through the radio frequency electric field applied between the electrode that acts as a support for the wafer and a larger counter electrode that typically completely envelops the first electrode. Known as reactive ion etching (RIE), the attack of the oxide in a plasma by reactive ions (radicals), typically F-, activated by bombardment of the surface being treated; It is an established technique to perform the removal of oxides or similar non-conducting materials corresponding to pre-formed pores in a masking material by techniques described in US Pat.

The desired anisotropy of the chemical attack of the oxide is necessarily determined by the directionality of the partial bombardment of the ions, which occurs perpendicular to the wafer surface through the pores of the window, and the method You can continue until you do.

After such a zone-defining method, the wafer is introduced into an apparatus for metallization, which is generally carried out with sputtering techniques. According to such techniques, atoms of a selected metal are ejected from the surface of a solid metal bombarded with ions of an inert gas accelerated in a radio frequency electric field, generally in a thin and extremely uniform layer. Deposit on the entire surface of the chamber covering the wafer.

It is also known that this is followed by a heat treatment of the metallized wafer at a temperature and time sufficient to favor the formation of a metallurgical alloy between the deposited metal and the single crystal semiconductor corresponding to the zones of connection. It is being

In a connection formed by this method without any other special measures, the connection resistance is strongly influenced by the surface condition of the semiconductor single crystal (for example silicon). The presence of a silicon oxide residue after an attack to remove the oxide layer from the area intended for connection and/or easily reaches a depth or thickness of about 50 nm at room temperature Continuous reoxidation of the silicon surface in contact with the atmosphere, the presence of a film of polymerizable substances formed on the semiconductor surface during the attack by CxFy or possibly CxHyFz, the loss of hydrogen atoms in the crystal structure of silicon, "Implantation" are several factors that cause the connection resistance to be relatively high.

Furthermore, the connection resistance is critically influenced by the state of the silicon crystal lattice near the surface of the connection as well as the metallized layers.

The step of removing the non-conducting, typically 5 in 2 layer is as described above by bombardment with ions strongly accelerated by a radio frequency electric field until the kinetic energy reaches a range varying from about 100 eV to about 5 KeV. is influenced almost exclusively by the way in which it is planned.

The silicon crystal next to the surface is significantly damaged by this impact treatment, and this damage is manifested by dislocations, lattice defects and other active centers occurring in the crystal lattice near the damaged surface, and this fact tends to increase connection resistance. After further exposure to the atmosphere, a thin oxide layer, which can reach a thickness of approximately 50 nm, rapidly forms on the silicon surface thus exposed, and the oxidation is similar to that of the previous RIE.
The presence of process-induced defects in the silicon single crystal favors a very favorable process on the surface.

The removal of these impurities, such as incidental oxide films and/or polymeric substances due to reoxidation in the air, is recommended for the purpose of reducing the connection resistance caused by various phenomena of contamination of exposed surfaces of silicon. The wafer is typically bathed with argon ions (Ar) inside the metal deposition chamber itself before proceeding with sputtering deposition.
It has been proposed to proceed by a simple sputtering etching process through bombardment with non-reactive ions (")".

This technique makes it possible to avoid the presence of oxides or other contaminants at the interface between the semiconductor and the metallized layer, but on the other hand to avoid the presence of crystals near the interface of the connection. This is in addition to the damage caused by the previous RIE attack which determines the conditions leading to relatively high connection resistance.

OBJECTS OF THE INVENTION It is an object of the invention to provide an improved method and apparatus for forming ohmic connections between metals and semiconductors.

Essentially, the inventive method actively reduces sources of excessive voltage drops and other negative effects due to connection resistance often observed in ohmic connections made by known techniques between metals and semiconductors. Allows the formation of ohmic connections.

According to the method of the invention, a single portion of otherwise contaminated semiconductor material in a defined area for the formation of a possible thin surface oxidation layer and/or ohmic contact is obtained before proceeding with metal deposition. The crystalline layer and the immediately underlying monocrystalline layer with a certain thickness, i.e. the surface layer of the crystal damaged by a previous step of the method for manufacturing the device or integrated circuit, are removed by plasma etching.

At this stage the crystal, whose thickness is preferably between 200 and 500 mm, is removed to ensure substantial removal of the damaged parts of the crystal itself.

The wafer treated in this way is introduced into a chamber for metal deposition without contact with an oxidizing atmosphere, thereby preventing possible re-oxidation of the etched surface. Sputtering deposition of metal layers for connection is then carried out according to conventional techniques on a number of wafers so prepared.

Dry attack (plasma etching) is a chamber conveniently equipped with an entrance door for introducing the wafer and a transfer door for moving the processed wafer into the sputtering chamber, which can be under reduced pressure for plasma etching. It happens inside. The interior of the chamber is made of a material that is resistant to the chemical reagents used in the method. Stainless steel and alumina clad aluminum alloys are some examples of suitable materials.

There are two electrodes in the plasma etching chamber. the first movable electrode has a flat plate on which one or more wafers to be processed are placed;
The plate has a counter electrode (forming part of a cap or box) which preferably receives the first electrode corresponding to its bottom hole so that the plasma is preferably confined between the two electrodes during processing. generally connected to the earth). Once the wafer is introduced, the chamber is first evacuated to about 10-' to 10-'' Torr and then sulfur hexafluoride (SF4) or nitrogen trifluoride (NF3) is introduced, preferably for an additional 150 A small amount of oxygen, ranging from 5 to 30% by volume, is introduced at a pressure of up to 350 milliTorr.

A radio frequency (RF) electric field is then applied to the electrode, typically with a peak-to-peak voltage of between about 200 and 500 volts with a frequency of 13.56 MHz, by an RF oscillator with a power of about 200 to 500 W. do.

SF or NF3 gas is ionized and its half-life (
During the half period) the electrode on which the wafer rests is positive and the anion F is accelerated and bombards the surface of the wafer, where it forms volatile compounds which are brought under reduced pressure by (for example) a vacuum pump system. It combines with the silicon on the exposed surface of the crystal.

The method of chemical attack activated by RF energy (plasma etching) typically removes between 200 and 500 silicon of sufficient thickness to produce a relatively isotropic pattern without causing damage to the crystal lattice. etching the silicon surface in a conventional manner, thereby removing the oxidation of the surface parts of the single crystal damaged by the previous treatment for removal of the oxide layer by RIE attack, and with it trace amounts of polymer or other contaminant elements. Removal of objects is ensured.

Silicon attack occurs according to two possible reactions:

a) SF6 +Oz+5i-SiF4+5iFx+
5xOyFzb) NFI +0. +Si−+SiF4
+5iFx+Nx0yFz Preferably at this point, the chamber is completely purged to the etching atmosphere, the door communicating with the vacuum sputtering chamber is opened, the electrode is lowered, and a suitable mechanism sputters the processed wafer from the electrode surface. It is moved to the chamber and the intercommunication door is closed again.

The entrance or access door is opened and another wafer is introduced into the plasma etching chamber and the process is repeated again. The sputtering chamber is capable of accommodating from 8 to 15 wafers, depending on the wafer diameter, and once loaded, metal deposition by sputtering is performed according to known techniques.

For a better understanding of the invention, the description of the relevant apparatus will continue with reference to the accompanying drawings, in which: FIG.

Figure 1 of the drawings is a schematic diagram showing an embodiment of the apparatus of the present invention, and Figure 2 is a schematic sectional view of the plasma etching chamber of Figure 1.

As can be seen in FIG. 1, the apparatus consists of a sputtering chamber 1 and a plasma etching chamber 2, which are adjacent to each other for operation.

The plasma etching chamber 2 constitutes a pre-chamber of the spacing chamber 1, and a high vacuum door 3, indicated schematically at 3, connects the two chambers. The prechamber 2, the plasma etching chamber, is fitted with a second high vacuum door 4, indicated schematically at 4, for introducing the wafer to be processed.

The chambers 1 and 2 can each be independently brought to a reduced pressure through respective high pressure reduction valves communicating them with a reduced pressure generation plant.

In FIG. 2, a cross-sectional view of the plasma etching chamber 2 of FIG. 1 is schematically shown.

The inner walls of the chamber are preferably made of stainless steel or other suitable material that is resistant to the reagents used.

An electrode or screen 6 shaped like a cap and substantially covering the top of the chamber space is made of stainless steel and is connected to earth.

A second electrode 7 formed of an Al2O3 or stainless steel plate is connected to the R through a supporting conducting stem 8 which is sealed with a suitable high vacuum seal and penetrates the bottom wall of the chamber.
It is connected to a source of F energy.

The electrode 7 can be moved vertically between the two positions shown.

The wafers to be metallized are introduced one by one through the entrance or access door 4 and placed on the plate 7. After raising the electrode 7 to its operating position (indicated by the dotted line 7° in FIG. 2), the entrance door 4 is closed again. The chamber is then evacuated to about 10-' to 10-' Torr and SF6 and NF3 and oxygen gases are introduced to a pressure of 150 to 350 millitorr.

An RF electric field is then applied between the two electrodes 6 and 7, and the plasma etching is continued for a period sufficient to remove about 200 to 500 semiconductor materials, typically 10 to 200 seconds.

At this point the power is interrupted, the electrode 7 is lowered, the interconnecting door 3 with the sputtering chamber is opened, and a mechanism (not shown) moves the processed wafer through the door 3 from the chamber 2 to the chamber 1. After closing the door 3 again, the door 4 is opened again to allow a new wafer to be introduced into the plasma etching chamber 2 and further operation to be continued.

A certain number of wafers are placed in sputtering chamber 1.
The metallization is carried out according to the usual procedures for metallization operations, and the metallized wafer is then heat treated to deposit the metal and single crystal semiconductor material correspondingly at the connecting interface. An alloy is formed in between.

(Effects of the Invention) The present invention provides the final "
"stripping" ensures that accidentally damaged or contaminated surfaces are removed and prevented from contacting oxidizing atmospheres prior to further metal deposition. Therefore, ohmic-connected metal-semiconductor connections made in accordance with the present invention exhibit consistently lower resistances compared to connections made in accordance with the prior art, thereby significantly reducing power dissipation and/or improving operating characteristics. Provide improved device reliability.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing one embodiment of the apparatus of the present invention, and FIG. 2 is a schematic cross-sectional view of the plasma etching chamber of FIG. 1. 1... Sputtering chamber 2... Plasma etching chamber 3.4... High vacuum door 6.7.7'... Electrode 8... Conductive stem

Claims (1)

[Claims] 1. A single crystal of semiconductor material in a lower part corresponding to a section for forming an ohmic connection between the semiconductor single crystal and a layer of metal deposited on the surface of the wafer. metal in a semiconductor device essentially represented by a wafer of single crystal semiconductor material having a surface at least partially covered with a layer of non-conducting material through which holes are formed for exposing the surface; In a method of forming an ohmic connection between semiconductor materials, a single crystal of semiconductor material corresponding to said section removes a portion of the single crystal that was damaged during formation of said hole in said layer of non-conducting material. A method characterized in that a layer of metal is deposited on the surface of a wafer that is plasma etched to a depth sufficient to remove the semiconductor material and to prevent the etched surface of the semiconductor material from coming into contact with an oxidizing atmosphere. 2. A method as claimed in claim 1, characterized in that the plasma etching is continued until a single crystal of semiconductor material is removed with a thickness of 200 to 500 Å. 3. Plasma etching at 150 to 350 mm Torr
3. A process according to claim 1, wherein the process is carried out in SF_6 or NF_3 in the presence of oxygen at a pressure up to r. 4. The method according to any one of claims 1 to 3, wherein the formation of holes in the layer of non-conducting material is performed by RIE attack of the non-conducting material until the semiconductor material is exposed. Method. 5. The semiconductor material is silicon doped with P or N,
5. A method according to any of claims 1 to 4, wherein the non-conductive material is silicon dioxide. 6. having an evacuable sputtering chamber into which the wafer to be metallized is placed;
an apparatus for depositing a metal layer on a wafer of semiconductor material having a defined section by masking and RIE attack to form an ohmic connection between the metal and the semiconductor, adjacent to the sputtering chamber;
a depressurizable plasma etching chamber connected to the sputtering chamber by a high vacuum door and having another access or inlet high vacuum door for introducing a wafer; and independently depressurizing the sputtering chamber and the plasma etching chamber. and means capable of operating under reduced pressure to transport a wafer from the plasma etching chamber to the sputtering chamber.