GB2181297A - Process and apparatus for making ohmic contacts between metal and semiconductor - Google Patents

Process and apparatus for making ohmic contacts between metal and semiconductor Download PDF

Info

Publication number
GB2181297A
GB2181297A GB08620131A GB8620131A GB2181297A GB 2181297 A GB2181297 A GB 2181297A GB 08620131 A GB08620131 A GB 08620131A GB 8620131 A GB8620131 A GB 8620131A GB 2181297 A GB2181297 A GB 2181297A
Authority
GB
United Kingdom
Prior art keywords
semiconductor
metal
semiconductor material
layer
chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08620131A
Other versions
GB8620131D0 (en
GB2181297B (en
Inventor
Giulio Iannuzzi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Microelettronica SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Microelettronica SpA filed Critical SGS Microelettronica SpA
Publication of GB8620131D0 publication Critical patent/GB8620131D0/en
Publication of GB2181297A publication Critical patent/GB2181297A/en
Application granted granted Critical
Publication of GB2181297B publication Critical patent/GB2181297B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A process and apparatus for making ohmic contacts between metal and semiconductor material in semiconductor devices such as integrated circuits is disclosed. The process contemplates the preventive removal of a superficial layer of the semiconductor, corresponding to the areas which will receive the contacts, by plasma etching in order to remove the portion of the crystal damaged by the preceding steps for the definition of the areas. The process is carried out in an apparatus comprising a sputtering chamber (1) and an adjacent plasma etch pre-chamber (2). <IMAGE>

Description

SPECIFICATION Process and relative apparatus for making ohmic type contacts between metal and semiconductor The present invention concerns an improved process and relative apparatus for making ohmic contacts between metals and semiconductors, in particular P or N doped silicon.
In the fabrication of any integrated circuit, so as in the fabrication of any semiconductor device, accord- ing to the most different techniques used for making such devices, for example, by the method of the grown junction, alloy junction, planartechnology, Planox (a registered trade mark ofthe company SGS Microelettronics S.p.A. - Italy) technology etc., it is necessarytoform ohmic type contacts between the semiconductor material, for example silicon doped P or N, and the metallic material used for creating, for example, the required interconnections on the "front" side of the integrated circuit orforthe connection to the support on the "rear" of the same.
The metallic material used may be of different kind aluminium, tungsten, platinum, alloys thereof, nitrides, silicides and heavily doped polycrystalline silicon are examples of suitable materials used commercially.
This type of contact which is formed between the material having metallic conduction and the semiconductor material must show an essentially linear and symmetric about the origin current-voltage characteristic (ohmic contact), that is it must not bring about phenomena of "rectification" of the current neither noticeable non-linearities at least within a certain portion (maximum foreseeable intensity of the operating current) of the characteristic about the origin ofthe axes at the foreseeable conditions of operation (temperature, radiation etc.) for the device.
Moreover, the contact resistance mustbethe lowest possible for obvious reasons of power dissipation, switching times, etc.
Commonly, according to the known modern tech niques, the process for forming such contacts on wafers onto which have already been made the necessary diffusions and after having reformed the superficial insulating layer of oxide orof an equivalent dielectric compound; applied a new layer of photeresist and having formed through it the required "windows" by the known photolitographictechniquesfor masking; contemplates that the removal of the dielectric material layer, commonly oxide (e.g.
SiO2), in correspondence of the windows formed in the layer of photoresist until exposing the semiconductor (e.g. doped silicon), take place undersub stantiallyanisotropicconditions, or anywaycon- trolled conditions, in order to insure a good definition of the dimensions of the areas onto which the ohmic contact will be formed.
It is therefore an established technique to carry out the removal of the oxide or ofthe similar dielectric material, in correspondence ofthe pre-formed apertures in the masking material by means of a tech nique known as Reactive Ion Etching (briefly RIE), that is by means of an attack of the oxide in plasma with reactive ions (radicals), typically F-, activated by the bombardment to which the surface of the oxide is subjected by part of ions accelerated through a radiofrequency electric field applied between an electrode acting as the support for the wafers and a counterelectrode of larger dimensions which, typically, completely envelops the first electrode.
The desired an isotropy of the chemical attack of the oxide being determined by the directionality of the bombardment by part of the ions which takes place, necessarily, perpendicularly to the surface of the waferthrough the aperture ofthe window and the process is protracted until exposing the underlying single crystal semiconductor.
After such a process of definition of the areas, the wafers are introduced in the apparatus for metallization which is commonly effected by a sputtering technique. According to such a technique, atoms of the selected metal, released from the surface of the solid metal bombarded by ions of an inert gas accelerated in a radio-frequency electric field, deposit generally over all the surfaces of the chambercover- ing with a thin and extremely uniform layerthe wafers.
It is also known to proceed after this with a thermal treatment of the metallized wafers at a temperature and for a period oftime sufficient to favourtheform- ation of a metallurgical alloy between the deposited metal and the single crystal semiconductor material in correspondence of the areas of contact.
In contacts formed in this way, withoutfurtherspe- cial expedients, the contact resistance results strongly influenced by the condition of the surface of the semiconductor single crystal (e.g. silicon). The presence of residues of silicon oxide after the attack for removing the layer of oxide from the areas intended for the contacts, and/orthe successive reoxidation of the silicon surface in contact with the atmosphere for a depth orthickness which, at room temperature, may easily reach about 50 A, the pres- ence on the surface ofthe semiconductorofafilm of polymeric material formed during the attack by CxFy or possibly CxHyFz groups, "implantation" of hydrogen atoms in the crystal structure ofthe silicon are some ofthe factors which cause a relatively high contact resistance.
Further, the contact resistance is decisively influenced by the state of the crystal lattice ofthe silicon near the surface of contact with the metallization layer.
The step of removal of the layer of the dielectric, typically SiO2 is, as mentioned before, almost exclusively effected with methods which contemplate the bombardment with ions strongly accelerated by a radio4requencyelectricfield until reaching kinetic energies comprised in a range varing from about 100 eVto about 5 KeV.
The silicon crystal next to the surface is noticeably damaged by this bombardment treatment and the damage is evidenced by the generation of dislocations, lattice defects and otheractivecentres within the crystal lattice nearthe surface subjected to the bombardment which fact tends to increase the contact resistance. Furthermore upon exposure to the atmosphere, on the surface of the silicon thus exposed a thin layer of oxide is rapidly formed which may reach a thickness of about 50 ; the oxidation being strongly favoured, on the surface, by the presence in the silicon single crystal ofthe defects indu ced by the preceding RlEtreatment.
With the aim of reducing contact resistance caused bythevarious phenomena of contamination ofthe exposed surface ofthe silicon it has been proposed to proceed to removal ofthose impurities such as the eventual oxide film due to the re-oxidation in air and/or of polymeric material, by subjecting the wafers to a brief sputter etch treatmentthrough bombardmentwith non-reactive ions, commonly Argon ions (Ar+) inside the chamberforthe metal deposition itself, before proceeding to the deposition by sputtering ofthe metal.
This technique, though permitting to insure an almosttotal absence of oxide or of other contaminants atthe interface between the semiconductor and the metallization layer, introduces, on the other hand, a further damage by bombardment of the crystal near the contact interface which adds to the damage caused bythe preceding RIE attack determining conditions leading to a relatively high contact resistance.
It is an object of the present invention to provide an improved process and apparatus for making ohmic contacts between metal-semiconductor.
Essentially the process of the present invention allows forming contacts metal-semiconductor of ohmictype, positively reducing the causes of the excessive voltage drops and ofthe other negative effects attributable to the contact resistance which often are observed with the ohmic contacts formed according to the known art.
According to the process of the invention, before proceeding with the deposition of the metal, the possible thin superficial oxidized layer and/or otherwise contaminated layer of the single crystal of semiconductor material in the areas defined for the form- ation of the ohmic contacts, and a layer of a certain thickness of the single crystal immediately under neath,that is the superficial layer of the crystal damaged by the preceding steps ofthefabrication process of the device or integrated circuit, are removed by means of a plasma etch.
In this stage a thickness of the crystal preferably comprised between 200 and 500 A is removed thus insuring the substantial removal of the damaged portion of the crystal itself.
The wafer thus treated is directly introduced in the chamberforthe deposition ofthe metal without it coming into contact with the oxidizing atmosphere thus preventing any possible re-oxidation of the etched surface. The sputtering deposition ofthe metallic layerforthe contact is thence effected according to the common technique over a certain number of so pre-treated wafers.
The dry attack (plasma etch) takes place in a dedi cated evacuable chamber for plasma etch convenientely provided with an inlet doorforthe intro duction of the wafers and with a transfer doorforthe shifting ofthetreatedwafersintothesputtering chamber.
The interior ofthe chamber is made with materials resistant to the chemical reagents utilized in the pro cess. Stainless steel and aluminium alloys cladded with alumina are some examples of suitable materials.
In the plasma etch chamber there are two electrodes. Aflrst mobile electrode comprising a flat plate onto which is rested the wafer or wafers to be treated, which plateisthenceraiseabletowardsthecounter- electrode (generally connected to ground) which forms part of a cap or box suitable to receive the first electrode in correspondence of its bottom aperture in such awaythatthe plasma be suitably confined between the two electrodes during the treatment.
Once a wafer has been introduced the chamber is first evacuated until about 1 0-7 10-7- 10-3Torrandthan sulphur hexafluoride (SF6) or nitrigen trifluoride (NF3) is introduced and preferably it is also introduced a small amount of oxygen, comprised between 5 and 30% by volume, at a pressure comprised between 150 and 350 mTorr.
A radio-frequency (RF) electric field is thence applied to the electrodes, typically a peak-to-peakvoltage comprised between about 200 and 500 volts with a frequency of 13,56 MHz, by means of a RF generator having a power of about 200-500 W.
The gas SF6 or NF3 is ionized and the anion F-, during the half period in which the electrode on which the wafer is placed is positive, is accelerated to impact the surface of the wafer where it combines (for example) with the silicon of the exposed surface of the crystal forming volatile compounds which are evacuated by the vacuum-pump system.
The process of chemical attack, activated by the RF energy (plasma etch), etches the surface of the silicon in a relatively isotropic fashion without causing damages to the crystal lattice thus, by removing a sufficient thickness, commonly between 200 and 500 A of silicon, the removal of the superficial portion of the single crystal which had been damaged bythe preceding treatmentforthe removal of the layer of oxide by RIE attack is insured and with it any trace of oxide, of polymer or of other contaminating element.
The attack of silicon takes place according to the following two possible reactions: a) SF6 + 02 + Si- SiF4 + SiFx + SxOvFz b) NF3 + 02 + Si- #SiF4+ SiFx+ SiFx + NxOyFz Preferably, atthis point,the chamber is completely purged of the etching atmosphere, the door communicating with the evacuated sputtering chamber is opened,the electrode lowered and a suitable mechanism shiftsthetreatedwaferfromthesurface of the electrode to the sputtering chamber and the intercommunicating door is closed again.
The inlet or access door is opened and another wafer may be introduced into the plasma etch chamber to repeat the process. The capacity ofthe sputtering chamber is generally comprised between 8 and 15 wafers depending upon their diameter and, when the load is completed, the sputter deposition of the metal is performed according to the known art.
For a better comprehension of the invention the description proceeds now with the illustration of the relative apparatus making reference to the annexed drawings wherein: Figure lisa schematic diagram ofthe apparatus of the invention; Figure 2 is a schematic section of view ofthe plasma etch chamber of Figure 1.
As it may be observed in Figure 1, the apparatus comprises a sputtering chamber 1 and a plasma etch prechamber 2 placed operatively one next to the other.
The plasma etch chamber 2 constitutes a pre chamberofthe sputtering chamber 1 and a high vacuum door, schematically indicated with 3, interconnects the two chambers. The plasma etch chamber, that is the pre-chamber 2, is provided with a second high vacuum door, schematically indicated with 4, for the introduction of the wafers to be treated.
The chambers 1 and 2 are independently evacuablethrough respective high vacuum valves which place them in communication with the vacuum generating plant or plants.
In Figure 2 is schematically shown a section ofthe plasma etch chamber 2 of Figure 1.
The interior walls ofthe chamber are made preferably of stainless steel or other suitable material re sistant to the reagents utilized.
An electrode or screen 6 shaped as a cap and which covers essentiallythetop portion of the cavity of the chamber is made of stainless steel and is connected to ground.
A second electrode 7, formed by a plate of Awl203 or of stainless steel, is connected to the source of RF energy through a supporting conductive stem 8 which passes through the bottom wall ofthe chamberthrough a suitable high vacuum seal.
The electrode 7 may be vertically shifted to the two positions shown.
The wafers to be metallized are introduced one by one through the inlet or access door4 and placed on the plate 7. After the electrode 7 is raised to its working position (indicated bythe phantom Figure 7' in Figure 2) and the inlet door 4 is closed again. The chamber is thence evacuated to about 10-7 - 1 10-8 Torr and SFG or NFB and oxygen gas is introduced ata pressure comprised between 150 and 350 mTorr.
The RFfield is thence applied between the electrodes 6 and 7 and the plasma etch is continued for a time sufficient to cause the removal of about 200 500 A of semiconductor material, generally comprised between 10 and 200 seconds.
At this point power is interrupted, the electrode 7 is lowered, the door 3 of interconnection with the sputtering chamber is opened and a mechanism (not shown) shifts the treated wafer from the chamber 2 to the chamber 1 through the door 3. Afterthe door 3 is closed again and the door 4 is re-opened for allowing introduction of a new wafer into the plasma etch chamber 2 and so on.
When a certain numberofwafers has been accumulated in the sputtering chamber 1,the metallization is effected according to the normal procedures for such an operation; after, the metallized wafers maybe heat treated to form a metallurgical alloy between the deposited metal and the semiconductor material ofthe single crystal in correpondence ofthe contact interface.
The ohmic contacts metal-semiconductorformed in accordance with the present invention consistently show a lower resistance in comparison to the contacts formed according to the prior art thus providing a noticeable reduction ofthe powerdissipationi and/or an improvement of the dynamic char acteristics and ofthe reliability of the devices.

Claims (8)

1. A process for making ohm ic type contacts be- tween metal and semiconductor in semiconductor devices, essentially represented by a wafer of a single crystal semiconductor material having at least a surface partially covered by a layer of dielectric material through which layer have been formed apertures such to expose the surface of the single crystal of semiconductor material underneath in correspondence of areas for the formation of ohmic type contacts between the semiconductor single crystal and a layer of metal deposited on the surface ofthe wafer, characterized in that the single crystal of semiconductor material, in correspondence of said areas, is plasma etched for a depth sufficientto removethe portion of the single crystal damaged during the formation of said apertures in said layerofdielectric material and the layer of metal is deposited on the surface of the wafer preventing the contact of the etched surface of the semiconductor material with an oxidizing atmosphere.
2. The process of claim 1 wherein the plasma etching is continued until removing a thickness of the single crystal of semiconductor material comprised between 200 and 500 A.
3. The process of claim 1 wherein the plasma etching is effected in SFG or NFB in presence of oxygen at a pressure comprised between 150 and 350 mTorr.
4. The process of claim 1 wherein the formation of said apertures in said layer of dielectric material is effected by RIE attack of the dielectric material until exposing the semiconductor material.
5. The process of claim 1 wherein the semiconductor material is P or N doped silicon and said dielectric material is silicon dioxide.
6. Apparatusforthedeposition of a metal layer on wafers of semiconductor material having areas, defined by masking and RIE attack, destined to the formation of ohmic type contacts between metal and semiconductor comprising an evacuable sputtering chamber into which are placed the wafers to be metallized, characterized by comprising an evacuable chamber of plasma etch next to said sputtering chamber and in communication with the latter through a high vacuum door; said plasma etch chamber being provided with another high vacuum door of access or inlet for the introduction ofthe wafers; means for independently evacuating said sputtering chamber and said plasma etch chamber and means, operable under vacuum, capable of transfering the wafers from said plasma etch chamberto said sputtering chamber.
7. A process for making ohmic type contacts between metal and semiconductor substantially as hereinbefore described with reference to the accompanying drawings.
8. Apparatus for the deposition of a metal layer on wafers of semiconductor material, substantially as hereinbefore described with reference to, and as shown in, the accompanying drawings.
GB8620131A 1985-10-01 1986-08-19 Process and relative apparatus for making ohmic type contacts between metal and semiconductor Expired GB2181297B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT22325/85A IT1185964B (en) 1985-10-01 1985-10-01 PROCEDURE AND RELATED EQUIPMENT TO MAKE OHMIC METAL-SEMICONDUCTOR CONTACTS

Publications (3)

Publication Number Publication Date
GB8620131D0 GB8620131D0 (en) 1986-10-01
GB2181297A true GB2181297A (en) 1987-04-15
GB2181297B GB2181297B (en) 1989-06-07

Family

ID=11194694

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8620131A Expired GB2181297B (en) 1985-10-01 1986-08-19 Process and relative apparatus for making ohmic type contacts between metal and semiconductor

Country Status (6)

Country Link
JP (1) JPS6286716A (en)
DE (1) DE3633472A1 (en)
FR (1) FR2588120A1 (en)
GB (1) GB2181297B (en)
IT (1) IT1185964B (en)
NL (1) NL8602453A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430303A2 (en) * 1989-12-01 1991-06-05 Applied Materials, Inc. Improved process for selective deposition of tungsten on semiconductor wafer
EP0448763A1 (en) * 1990-03-30 1991-10-02 Siemens Aktiengesellschaft Process and apparatus for manufacturing conductive layers or structures for highly integrated circuits
EP0452889A2 (en) * 1990-04-16 1991-10-23 Applied Materials, Inc. Process for forming titanium silicide on a semiconductor wafer
US5478780A (en) * 1990-03-30 1995-12-26 Siemens Aktiengesellschaft Method and apparatus for producing conductive layers or structures for VLSI circuits

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4339465C2 (en) * 1993-11-19 1997-05-28 Gold Star Electronics Process for treating the surface of a silicon substrate exposed to dry etching

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1177382A (en) * 1966-02-24 1970-01-14 Rca Corp Formerly Known As Rad Method of Making Ohmic Contact to a Semiconductor Body
GB1279229A (en) * 1969-11-03 1972-06-28 Rca Corp Method of metalizing semiconductor devices
GB1410701A (en) * 1972-01-03 1975-10-22 Signetics Corp Schottky barrier diode semiconductor structures
GB1530237A (en) * 1976-05-14 1978-10-25 Data General Corp Method of fabricating metal semiconductor interfaces
EP0057254A2 (en) * 1981-02-03 1982-08-11 Siemens Aktiengesellschaft Method of producing extremely fine features

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4107835A (en) * 1977-02-11 1978-08-22 Bell Telephone Laboratories, Incorporated Fabrication of semiconductive devices
JPS57157525A (en) * 1981-03-23 1982-09-29 Fujitsu Ltd Surface treating method
JPS6077429A (en) * 1983-10-04 1985-05-02 Asahi Glass Co Ltd Dry etching method
US4693777A (en) * 1984-11-30 1987-09-15 Kabushiki Kaisha Toshiba Apparatus for producing semiconductor devices
US4824518A (en) * 1985-03-29 1989-04-25 Sharp Kabushiki Kaisha Method for the production of semiconductor devices
US4605479A (en) * 1985-06-24 1986-08-12 Rca Corporation In-situ cleaned ohmic contacts

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1177382A (en) * 1966-02-24 1970-01-14 Rca Corp Formerly Known As Rad Method of Making Ohmic Contact to a Semiconductor Body
GB1279229A (en) * 1969-11-03 1972-06-28 Rca Corp Method of metalizing semiconductor devices
GB1410701A (en) * 1972-01-03 1975-10-22 Signetics Corp Schottky barrier diode semiconductor structures
GB1530237A (en) * 1976-05-14 1978-10-25 Data General Corp Method of fabricating metal semiconductor interfaces
EP0057254A2 (en) * 1981-02-03 1982-08-11 Siemens Aktiengesellschaft Method of producing extremely fine features

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430303A2 (en) * 1989-12-01 1991-06-05 Applied Materials, Inc. Improved process for selective deposition of tungsten on semiconductor wafer
EP0430303A3 (en) * 1989-12-01 1992-10-28 Applied Materials, Inc. Improved process for selective deposition of tungsten on semiconductor wafer
EP0448763A1 (en) * 1990-03-30 1991-10-02 Siemens Aktiengesellschaft Process and apparatus for manufacturing conductive layers or structures for highly integrated circuits
US5478780A (en) * 1990-03-30 1995-12-26 Siemens Aktiengesellschaft Method and apparatus for producing conductive layers or structures for VLSI circuits
EP0452889A2 (en) * 1990-04-16 1991-10-23 Applied Materials, Inc. Process for forming titanium silicide on a semiconductor wafer
EP0452891A2 (en) * 1990-04-16 1991-10-23 Applied Materials, Inc. Process for forming titanium silicide on a semiconductor wafer
EP0452888A2 (en) * 1990-04-16 1991-10-23 Applied Materials, Inc. Process for forming a layer of titanium silicide on a semiconductor wafer
EP0452891A3 (en) * 1990-04-16 1992-01-22 Applied Materials, Inc. Process for forming titanium silicide on a semiconductor wafer
EP0452888A3 (en) * 1990-04-16 1992-01-22 Applied Materials, Inc. Process for forming a layer of titanium silicide on a semiconductor wafer
EP0452889A3 (en) * 1990-04-16 1992-01-22 Applied Materials, Inc. Process for forming titanium silicide on a semiconductor wafer

Also Published As

Publication number Publication date
DE3633472A1 (en) 1987-04-02
JPS6286716A (en) 1987-04-21
IT8522325A0 (en) 1985-10-01
IT1185964B (en) 1987-11-18
NL8602453A (en) 1987-05-04
GB8620131D0 (en) 1986-10-01
FR2588120A1 (en) 1987-04-03
GB2181297B (en) 1989-06-07

Similar Documents

Publication Publication Date Title
US5232871A (en) Method for forming a titanium nitride barrier layer
US6511575B1 (en) Treatment apparatus and method utilizing negative hydrogen ion
US5175126A (en) Process of making titanium nitride barrier layer
US5882488A (en) Resputtering to achieve better step coverage
US5445710A (en) Method of manufacturing semiconductor device
US5203957A (en) Contact sidewall tapering with argon sputtering
US5416048A (en) Method to slope conductor profile prior to dielectric deposition to improve dielectric step-coverage
EP0219465B1 (en) Improved (rie) plasma etch process for making metal-semiconductor ohmic type contacts
US6793735B2 (en) Integrated cobalt silicide process for semiconductor devices
KR100838502B1 (en) Method of producing semiconductor device
US6335284B1 (en) Metallization process for manufacturing semiconductor devices
GB2181297A (en) Process and apparatus for making ohmic contacts between metal and semiconductor
EP0133452B1 (en) Reactive ion etching method
JPH11168090A (en) Semiconductor manufacturing method
US5855689A (en) Method for etching inside of tungsten CVD reaction room
JPH0722393A (en) Dry etching equipment and method
US20010049192A1 (en) Method and system for selectively coupling a conductive material to a surface of a semiconductor device
JP3619030B2 (en) Plasma processing apparatus and processing method
US6756315B1 (en) Method of forming contact openings
JPS628512B2 (en)
JP3239460B2 (en) Forming connection holes
KR100351906B1 (en) Method for fabricating of semiconductor device
Nam et al. Physical damage and contamination by magnetized inductively coupled plasmas and effects of various cleaning and annealing methods
EP0260232B1 (en) Process for making metal-semiconductor ohmic contacts
KR960008523B1 (en) Metal wiring method of semiconductor device

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20030819