JPS628562A - Beam lead type schottky barrier diode and manufacture thereof - Google Patents

Beam lead type schottky barrier diode and manufacture thereof

Info

Publication number
JPS628562A
JPS628562A JP60147293A JP14729385A JPS628562A JP S628562 A JPS628562 A JP S628562A JP 60147293 A JP60147293 A JP 60147293A JP 14729385 A JP14729385 A JP 14729385A JP S628562 A JPS628562 A JP S628562A
Authority
JP
Japan
Prior art keywords
layer
electrode
high conductivity
schottky
beam lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60147293A
Other languages
Japanese (ja)
Inventor
Kimihiko Nagami
永見　公彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP60147293A priority Critical patent/JPS628562A/en
Publication of JPS628562A publication Critical patent/JPS628562A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Abstract

PURPOSE:To form a diode with an N<++> type GaAs high conduction layer and the thin film of a GaAs operating layer, by providing an isolating layer comprising GaSlAs, and etching and removing only a GaAs semiconductor substrate without corroding the N-type GaAs operating layer. CONSTITUTION:On a GaAs substrate 1, a non-doped GaAlAs layer 2 as an isolating layer, an N-type GaAs operating layer 3 and N<++> type GaAs high conduction layer 4 are grown. An ohmic electrode 5 comprising Au-Ge-Ni is evaporated thereon. Then a glass plate having a pattern is bonded to the side of a second beam lead electrode 7 with resist 9. Thereafter, various kinds of etchings are carried out, and the high conduction layer 4 and the operating layer 3 beneath the ohmic electrode 5 are made to remain. Then, a polyimide film 10 is applied. Etching is performed, and a contact hole 10' is formed. A Schottky electrode 11 comprising Ti-Pt-Au is evaporated, and the unnecessary part of the polyimide film 10 is removed. Then, a first beam lead electrode electrode 12 is formed.

Description

【発明の詳細な説明】 イ）産業上の利用分野 本発明は化合物半導体を用いた超高周波用のビームリー
ド型ショットキバリヤダイオードに関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a beam-lead Schottky barrier diode for ultra-high frequencies using a compound semiconductor.

ロ）従来の技術 従来からショットキ障壁による高周波用、特にマイクロ
波に用いられるダイオードが多数提案されている。なか
でもビームリード型のもの（例えば特開昭５６−１３４
７８０号公報参照）は、パッケージ型のものに較べてワ
イヤボンディング工程が容易に行なえ特性の向上が図ら
れている０従来のビームリード型シ、ットキパリャダイ
オードの概略を第３図に示す。（１１は半導体基板で順
にｎ＋＋　型高伝導層（４）、ｎ型動作層（３）がエピ
タキシャル成長されている。ショットキ電極αυは前記
が掘込まれ、前記高伝導層（４）が露出した位置に形成
され、更にポリイミド膜（６）によって前記動作層ビー
ムリード電極、（７）が夫々前記ショットキ電極る０ 斯様な従来のビームリード型シーツトキバリャダイオー
ドの構造では、シ智ットキ電極αυからオーミック電極
（５′）までの距離が長く、特に高周波を扱うので表皮
効果により直列抵抗の低減は難しく、高伝導層（石の面
積が比較的大きいので、該高伝導層（４′）と第１ビー
ムリード電極（１２１間の寄生容量がダイオードの特性
に悪影響を及ぼしていた。B) Prior art Many diodes using Schottky barriers for use in high frequencies, especially microwaves, have been proposed in the past. Among them, beam-lead type ones (for example, JP-A-56-134
Figure 3 shows a schematic diagram of a conventional beam-lead-type cylindrical diode (see Japanese Patent Publication No. 780), in which the wire bonding process is easier and the characteristics are improved compared to the package-type one. . (11 is a semiconductor substrate on which an n++ type high conductivity layer (4) and an n type active layer (3) are epitaxially grown in order. The Schottky electrode αυ is located at the position where the above is dug and the high conductivity layer (4) is exposed. The active layer beam lead electrode (7) is formed by a polyimide film (6), and the Schottky electrode (7) is formed respectively by the Schottky electrode. The distance from the ohmic electrode (5') to the ohmic electrode (5') is long, and since we are dealing with high frequencies in particular, it is difficult to reduce the series resistance due to the skin effect. The parasitic capacitance between the first beam lead electrode (121) had an adverse effect on the characteristics of the diode.

ハ）発明が解決しようとする問題点 本発明は上述の点に鑑みてなされたもので、ビームリー
ド型ショットキバリヤダイオードの直列抵抗及び寄生容
量の低減化を図るものである。C) Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned points, and is intended to reduce the series resistance and parasitic capacitance of a beam lead type Schottky barrier diode.

二）問題点を解決するための手段 本発明は、半導体基板上に分離層、動作層及び高伝導層
を連続してエピタキシャル成長させ、該高伝導層上にオ
ーミック電極及びビームリード電極を形成した後に、前
記半導体基板及び分離層をそれぞれエツチング除去し、
前記動作層の前記オーミック電極と対向する表面にシ、
−ットキ電極が設けられ、更に該ショットキ電極からも
ビームリード電極が延在形成されているビームリード型
シ冒ットキパリアダイオードを得るものである。2) Means for Solving the Problems The present invention involves epitaxially growing a separation layer, an active layer, and a high conductivity layer in succession on a semiconductor substrate, and forming an ohmic electrode and a beam lead electrode on the high conductivity layer. , etching and removing the semiconductor substrate and the separation layer, respectively;
a surface of the active layer facing the ohmic electrode;
- A beam lead type Schottky parrier diode is provided with a Schottky electrode and further has a beam lead electrode extending from the Schottky electrode.

ホ）作　用 本発明のビームリード型シ１ブトキパリアダイオードで
は、ショットキ電極とオーミック電極との距離は動作層
と高伝導層の厚さになり、非常に短いものとなる。また
高伝導層の面積はオーミック電極の面積と略同じ大きさ
があれば良い事になる。E) Function In the beam-lead type single-button pariah diode of the present invention, the distance between the Schottky electrode and the ohmic electrode is equal to the thickness of the active layer and the high conductivity layer, and is therefore very short. Further, the area of the highly conductive layer should be approximately the same size as the area of the ohmic electrode.

へ）実施例 第１図は本発明によるビームリード型シ、ットキダイオ
ードの概略断面図であるｏ（３）はｎ型ＧａＡｓの動作
層、（４）は該動作層（３）上に成長されたｎ＋＋　　
型ＧａＡＳの高伝導層、（５１はＡｕ−Ｇｅ−Ｎ１から
なるオーミック電極、（１１１はＴｉ−Ｐｔ−Ａｕから
なるシ冒ットキ電極、（６）は絶縁膜としてのポリイミ
ド膜〜（７）は前記オーミック電極（５）から延在して
形成された第２ビームリード電極、（１２＋は前記ショ
ットキ電極Ｉから延在して形成された第１ビームリード
電極である０ 第１図に示す様にオーミック電極（５）とシ冒ットキ電
極（ＩＬｌは高伝導層（４）と動作層（３）を挾む位置
に設けられており、その間隔は１０μｍ程度と非常に短
くできる。また前記高伝導層（４）の面積も前記オーミ
ック電極（５）の面積（通常オーミック電極の面積の方
かシ冒ットキ電極の面積よりも広い）と同じくらいの大
きさにするφができる。即ち直列抵抗と寄生容量の低重
が図れる事になる０次に第２図Ａ乃至Ｇに沿って本発明
ダイオードの製造方法を説明する□ＧａＡｓ基板（１１
上に分離層としてのノンドープＧａＡ／Ａｓ層（２＋、
ｎ型ＧａＡａ動作層（３）及びｎ”ｆｆ１４ＧａＡａ高
伝導層（４）を連続エピタキシャル法で夫々厚さＱ、５
ｐｍ、　　α５μｍ及び１０μｍ成長させたウェハ（第
１図Ａ）にレジストを像布し通常のフォトリソグラフィ
技術及びリフトオフ法を用いて選択的にＡｕ−Ｇｅ−Ｎ
ｉからなるオーミック電極（５）を蒸着する０イはド股
（６）を前記オーミック電極（５］とのコンタクトホー
ル（１５）を得るようにヒドラジン系溶液でエツチング
する。そして前記レジストを除去しく第２図Ｂ）、第２
ビームリード電極（７）をＡｕの蒸着及び選択鍍金技術
にて形成する。次に第１図ＣＫ示す様に合わせパターン
のついたガラス板（８１ｔ−溶解除去できる接着剤（９
）（例えばレジスト）で前記第２ビームリード電極（７
）が形成された側ＶＣ接着するそしてアンモニア水と過
酸化水素水の混合液からなるエッチャントで前記ＧａＡ
ａ基板（１１をエツチング除去する。この時前記Ｇ　ａ
　ＡＩ　Ａ　ａ層（２；は全くエツチングされ、ない。(3) is an active layer of n-type GaAs, and (4) is a layer grown on the active layer (3). n++
High conductivity layer of type GaAS, (51 is an ohmic electrode made of Au-Ge-N1, (111 is a drying electrode made of Ti-Pt-Au, (6) is a polyimide film as an insulating film, and (7) is a A second beam lead electrode is formed extending from the ohmic electrode (5), (12+ is a first beam lead electrode formed extending from the Schottky electrode I), as shown in FIG. The ohmic electrode (5) and the insulating electrode (IL1) are provided at positions sandwiching the high conductivity layer (4) and the active layer (3), and the interval between them can be very short, about 10 μm. The area of the layer (4) can also be set to φ, which is about the same size as the area of the ohmic electrode (5) (usually larger than the area of the ohmic electrode or the area of the shield electrode). □GaAs substrate (11
A non-doped GaA/As layer (2+,
The n-type GaAa active layer (3) and the n”ff14 GaAa high conductivity layer (4) were formed by continuous epitaxial method to a thickness of Q and 5, respectively.
pm, α5 μm and 10 μm grown wafers (Fig. 1A) are coated with resist, and Au-Ge-N is selectively deposited using ordinary photolithography and lift-off techniques.
The ohmic electrode (5) consisting of I is vapor-deposited, and the dot (6) is etched with a hydrazine solution to form a contact hole (15) with the ohmic electrode (5).Then, the resist is removed. Figure 2B), 2nd
A beam lead electrode (7) is formed by Au vapor deposition and selective plating technology. Next, as shown in Figure 1 CK, a glass plate with a matching pattern (81t-adhesive that can be dissolved and removed (9)
) (e.g. resist) to the second beam lead electrode (7).
) is bonded to the side where the GaA is formed, and then the GaA
a substrate (11) is etched away. At this time, the Ga substrate (11) is removed by etching.
AI A a layer (2; is not etched at all.

そこで次にリン酸系エッチャントを用いて該ＧａＡｌ！
Ａ６層（２）をエツチング除去する。この場合も前記ｎ
型ＧａＡｓ動作層（３）はエツチングされずにエピタキ
シャル成長させた膜厚を保つ（第２図Ｄ）ｏ露出した動
作層（３）表面にレジストを塗布して、前記オーミック
電極（５）下の高伝導層（４）及び動作層（３）を残す
ように前記レジストをフォトリングラフィ技術で選択的
に形成し、酒石酸系エッチャントでパックメサエッチン
グを行い不用部分を除去して、前記レジストをも排除す
る（第２図Ｅ）。次に前述と同様にポリイミド膜部を塗
布し、更にレジストを塗って窓開けを行い、ヒドラジン
系溶液でエツチングしてコンタクトホールａイを形成す
る。Ｔｉ−Ｐｔ−Ａｕからなるショットキ電極ｔ１１１
を蒸着して、前記レジストを排除し、前記ポリイミド膜
０αの不用部分をも、　　エツチングに依り除去する（
第２図Ｐ）ｏそして第１ビームリード電極α２を選択鍍
金技術にて形成して、前記接着剤（９）を溶かして前記
ガラス板（８）を外しビームリード型ショットキバリヤ
ダイオードが完成される（第２図Ｇ）。Then, using a phosphoric acid etchant, the GaAl!
Etch and remove the A6 layer (2). In this case as well, the above n
The type GaAs active layer (3) is not etched and maintains the thickness of the epitaxially grown film (Fig. 2D). o A resist is applied to the exposed surface of the active layer (3) and the height below the ohmic electrode (5) is The resist is selectively formed using a photolithography technique so as to leave the conductive layer (4) and the active layer (3), and unnecessary portions are removed by pack mesa etching with a tartaric acid-based etchant, thereby also eliminating the resist. (Figure 2 E). Next, a polyimide film portion is applied in the same manner as described above, and a resist is further applied to form a window, and a contact hole a is formed by etching with a hydrazine solution. Schottky electrode t111 made of Ti-Pt-Au
The resist is removed by vapor deposition, and the unnecessary portion of the polyimide film 0α is also removed by etching (
FIG. 2 P)o Then, a first beam lead electrode α2 is formed by selective plating technology, the adhesive (9) is melted, and the glass plate (8) is removed to complete the beam lead type Schottky barrier diode. (Figure 2G).

ト）発明の効果 本発明は以ｊの説明から明らかな如く、ＧａＡ／Ａｓか
らなる分離層を介在させることによってｎ型ＧａＡ３か
らなる動作層を侵すことなくＧａＡ３の半導体基板だけ
をエツチング除去できるので、ダイオードがｎ＋“型Ｇ
ａＡａ高伝導層とｎ型ＧａＡｓ動作層の薄膜で構成が可
能となる。これにより、オーミック電極とシ、ツ１キ電
極の距離及び高伝導層の面積を小さくする事ができるの
で直列抵抗及び寄生容量の低減ｙ５１図れる。g) Effects of the Invention As is clear from the explanation in j below, the present invention allows only the GaA3 semiconductor substrate to be etched away without damaging the n-type GaA3 active layer by interposing the GaA/As separation layer. , the diode is n+“ type G
It is possible to construct a thin film consisting of an aAa high conductivity layer and an n-type GaAs operating layer. This makes it possible to reduce the distance between the ohmic electrode and the transparent electrode and the area of the highly conductive layer, thereby reducing series resistance and parasitic capacitance.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明ダイオードの概略断面図、第２図Ａ乃至
Ｇは本発明実施例の要部工程断面図、第３図は従来のビ
ームリード型ダイオード：の概略断面図である。FIG. 1 is a schematic sectional view of a diode of the present invention, FIGS. 2A to 2G are sectional views of main steps of an embodiment of the present invention, and FIG. 3 is a schematic sectional view of a conventional beam lead type diode.

Claims (1)

【特許請求の範囲】 １）動作層上の高伝導層表面にオーミック電極が設けら
れ、前記動作層の前記高伝導層が成長されていない前記
オーミック電極と対向する表面にショットキ電極が設け
られ、該ショットキ電極及び前記オーミック電極夫々か
らビームリード電極が延在して設けられている事を特徴
とするビームリード型ショットキバリヤダイオード。 ２）半導体基板上に分離層、動作層及び高伝導層をエピ
タキシャル成長させる工程と、該高伝導層上にオーミッ
ク電極を選択的に形成する工程と、該オーミック電極の
一部を残して前記高伝導層とともにその表面に高分子系
樹脂からなる絶縁膜を形成する工程と、前記オーミック
電極の露出している面にビームリード電極を選択的に形
成する工程と、前記半導体基板をエッチング除去する工
程と、前記分離層をエッチング除去する工程と、前記動
作層及び高伝導層を所望形状にエッチングする工程と、
前記分離層をエッチング除去することで露出した前記動
作層表面にショットキ電極を選択的に形成する工程と、
該ショットキ電極の表面一部を除いて前記動作層及び高
伝導層を高分子系樹脂からなる絶縁膜で覆う工程と、前
記ショットキ電極の露出している面にビームリード電極
を選択的に形成する工程とを含むことを特徴とするビー
ムリード型ショットキバリヤダイオードの製造方法。 ３）前記半導体基板はＧａＡｓから、前記分離層はＧａ
ＡｌＡｓからなる事を特徴とする特許請求の範囲第２項
記載のビームリード型ショットキバリヤダイオードの製
造方法。[Scope of Claims] 1) An ohmic electrode is provided on the surface of the high conductivity layer on the active layer, and a Schottky electrode is provided on the surface of the active layer opposite to the ohmic electrode on which the high conductivity layer is not grown; A beam lead type Schottky barrier diode characterized in that a beam lead electrode is provided extending from each of the Schottky electrode and the ohmic electrode. 2) A step of epitaxially growing a separation layer, an active layer, and a high conductivity layer on a semiconductor substrate, a step of selectively forming an ohmic electrode on the high conductivity layer, and a step of forming the high conductivity layer while leaving a part of the ohmic electrode. a step of forming an insulating film made of polymeric resin on the surface of the layer together with the layer; a step of selectively forming a beam lead electrode on the exposed surface of the ohmic electrode; and a step of etching away the semiconductor substrate. , a step of etching away the separation layer, and a step of etching the operating layer and the high conductivity layer into a desired shape;
selectively forming a Schottky electrode on the surface of the active layer exposed by etching away the separation layer;
a step of covering the active layer and the high conductivity layer with an insulating film made of polymer resin except for a part of the surface of the Schottky electrode; and selectively forming a beam lead electrode on the exposed surface of the Schottky electrode. A method for manufacturing a beam-lead Schottky barrier diode, comprising the steps of: 3) The semiconductor substrate is made of GaAs, and the separation layer is made of GaAs.
A method of manufacturing a beam-lead Schottky barrier diode according to claim 2, characterized in that the diode is made of AlAs.
JP60147293A 1985-07-04 1985-07-04 Beam lead type schottky barrier diode and manufacture thereof Pending JPS628562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60147293A JPS628562A (en) 1985-07-04 1985-07-04 Beam lead type schottky barrier diode and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60147293A JPS628562A (en) 1985-07-04 1985-07-04 Beam lead type schottky barrier diode and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS628562A true JPS628562A (en) 1987-01-16

Family

ID=15426929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60147293A Pending JPS628562A (en) 1985-07-04 1985-07-04 Beam lead type schottky barrier diode and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS628562A (en)

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