JPS6285327A - Microcomputer - Google Patents

Abstract

PURPOSE:To execute a count processing at a high speed by changing a size of a counter in accordance with a size of a count processing data, in a microcomputer provided with the counter. CONSTITUTION:When operating the titled microcomputer as an 8-bit counter, a connecting signal (a) is set to a '0' level and a higher rank nibble counter 4 and a lower rank nibble counter 5 are connected, and they are operated as the 8-bit counter. On the other hand, when operating said computer as a 4-bit counter, the connecting signal (a) is set to a '1' level the higher rank nibble counter 4 and the lower rank nibble counter 5 are separated and operated as independent counters, respectively. In this way, not only a count processing of a byte unit but also a count processing of a nibble unit can be executed at a high speed.

Description

[Detailed description of the invention] 〔overview〕 It's a microcomputer counter.

By operating it as a 4-bit counter or as an 8-bit counter, it has excellent versatility and enables high-speed counting processing.

[Industrial application field]

The present invention relates to a microcomputer, and more particularly to a microcomputer equipped with a counter that performs arithmetic processing.

[Conventional technology]

In conventional microcomputers, arithmetic processing is sometimes performed using an 8-bit counter.

For example, the original data is expressed in hexadecimal as A 3 (+6
1, and the count may be increased by one.

In this case, it is a normal increment operation, so if you input the data A 3 (+6) one byte at a time, increase the count of the lower byte by 1, and output it, you will get A 4 (16), and there is no problem, that is, the data The conventional 8-bit counter is effective when the data is processed in units of 8 bits (1 byte).

[Problems to be Solved by System No. 11] However, when processing is performed not in units of 1 byte but in units of 4 bits (1 nibble), there is a problem that the processing becomes complicated and the processing time increases. This will be explained using the flowchart shown in FIG.

Figure 2 shows the flow of processing when increasing the count of the original data A 3 (16) by 1 to B 3 (16>) using a conventional 8-bit count. There is.

First, shift data A3 (also data A3) to the right by 4 bits and OA
(16) 0 Next, the 8-bit counter increments the count by 1 to OB (161, and then shifts 4 bits to the left to BO (164).Meanwhile, in another flow, the original data A 3 (16 ) to the left by 4 bits to obtain 30 (1
After setting it to 61, it is further shifted to the right by 4 bits and becomes 03 (1
6).

Next, the logical sum of this 03(16) and the above-mentioned B O(16>) is obtained to obtain B3(16).

As described above, according to the conventional 8-bit counter, it is advantageous to increase or decrease the count for one byte, but when increasing or decreasing the count for one nibble, the problem is that the processing is complicated and the processing interval becomes long. There is.

The present invention was created in view of such conventional problems, and provides a microcomputer that enjoys a counter that has a compact configuration and can perform not only medium-byte counting operations but also nibble-degree counting operations at high speed. For the purpose of providing.

[To solve problems-Lllllffi) Unissued 11
The first 4-bit counter, the second 4-bit counter, and the first 4-bit counter and the second 4-bit counter are operated as an 8-bit counter by performing Ja k&. , or: 1IJ1 of 4
The present invention is characterized in that it includes a control circuit which separates the bit counter and the 4-bit counter of f42 and causes them to operate as independent 4-bit counters.

[Effect]

When counting in bytes, the control circuit connects the first 4-bit counter and the second 4-bit counter to operate as an 8-bit counter.

On the other hand, when counting in nipple degrees, the first 4-pin counter and the second 4-bit counter are separated by the control circuit and operated as independent counters.

Since the size of the counter can be changed in accordance with the size of processing data in this way, high-speed counting processing is possible.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a partial configuration diagram of a microcomputer according to an embodiment of the present invention, in which 1 is an accumulator, 2 is a first
3 is the second internal bus. 4 is an upper nibble counter whose input part is connected to the first internal bus 2 and whose output part is connected to the second internal bus, and increment counting or decrement counting is selected by I/D control signal C. 5 is a lower nibble counter whose input part is connected to the first internal bus 2 and whose output part is connected to the second internal bus 3; increment counting or decrement counting is selected by the I/D control signal e; , active signal d selects counting operation or non-operation.

6 is an OR circuit 7, an AND circuit 8, 9, and an input circuit 1
This is a control circuit consisting of 0, which controls the connection or separation of the CO output of the F-rank nibble counter 5 and the CI large input of the upper nibble counter 4 by the connect signal a, and connects the 1st-rank nibble counter to - via the active signal S. A count of 4 operation or non-operation controls.

The attached table is a truth table for explaining the operation of the embodiment of the present invention. When operating as an 8-bit counter, connect signal a is set to O level to connect upper nibble counter 4 and lower nibble counter 5, and active signal d is set to O level. When performing an increment operation, the I10 control circuits c and d are set to level, and when performing a decrement operation, the I/DM control signals c and d are set to O level.

Next, when operating as a 4-bit counter, the connect signal is set to all level to separate the upper nibble counter 4 and the lower nibble counter 5.

When operating the 1-place counter 4, the active signal S is further set to O level. When performing an increment operation, the I/D control signal C is set to L level, and when performing a decrement operation, the I/DM control signal d is set to θ level.

On the other hand, when operating the lower nibble counter 4, the active signal dftO level is set, when performing an increment operation, the I10 control signal e is set to level, and when performing a decrement operation, the 1/D control signal e is set to O level.

Next, a case will be described in which the count of the upper nibble of the data A 3 (16) of the accumulator 1 is increased by one using the counter according to the embodiment of the present invention.

The data A of the upper nibble in the accumulator l is input to the upper nibble counter 4, and the data 3 of the lower nibble is input to the lower nibble counter 4. At this time, the connect signal a is set to level, the active signal S is set to O level, the I10 control signal C is set to level, and the active signal d is set to 1.

As a result, the L-order nibble counter 4 performs an increment operation and outputs B, and the lower nibble counter 5 directly outputs 3 without performing a counter operation. Therefore, B 3 (+61) is obtained as the output of the counter.

As described above, according to the embodiment of the present invention, not only byte-by-byte counting processing but also nibble-by-nibble counting processing can be performed at high speed.

〔Effect of the invention〕

As described above, according to the present invention, the size of the counter can be appropriately changed in accordance with the size of the count processing data, so high-speed counting processing becomes IT-enabled.

[Brief explanation of drawings]

Figure 1 is book 9! FIG. 2 is a partial configuration diagram of a macrocomputer according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining problems in the conventional example. l...Accumulator 2...First internal bus 3...Second internal bus 4...Upper nibble counter 5...Lower nibble counter 6...1υI control circuit 7...OR circuit 8.9...AND circuit 10...Inverter circuit

Claims (1)

[Claims] A first 4-bit counter, a second 4-bit counter, and an 8-bit counter by connecting the first 4-bit counter and the second 4-bit counter according to an instruction. A microcomputer comprising: a control circuit for operating the first 4-bit counter and the second 4-bit counter as independent 4-bit counters;