JPS6282305A - Monitor pattern for measurint thickness of plating film - Google Patents
Monitor pattern for measurint thickness of plating filmInfo
- Publication number
- JPS6282305A JPS6282305A JP22440985A JP22440985A JPS6282305A JP S6282305 A JPS6282305 A JP S6282305A JP 22440985 A JP22440985 A JP 22440985A JP 22440985 A JP22440985 A JP 22440985A JP S6282305 A JPS6282305 A JP S6282305A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- thickness
- twice
- film thickness
- monitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は鍍膜厚測定用モニタパターン、特に、半導体装
置の金属配線、あるいは金属突起電極を鏝により成長、
形成する際、該鍍膜厚を測定するための鍍膜厚測定用モ
ニタパターンに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a monitor pattern for measuring coating film thickness, in particular, a method of growing a metal wiring of a semiconductor device or a metal protrusion electrode with a trowel.
The present invention relates to a coating thickness measurement monitor pattern for measuring the coating thickness during formation.
(従来技術)
一般に半導体装置に襞形成される金属配線、あるいは金
属突起電極は、一定の許容膜厚範囲内に収めることが必
要であり、膜厚を一定範囲内に収められないと、ピンホ
ールの発生、配線間の短絡等が生じ、半導体装置の機能
に重大な障害が生じる。(Prior art) Metal wiring or metal protruding electrodes that are generally formed with folds in semiconductor devices must be kept within a certain allowable film thickness range, and if the film thickness cannot be kept within a certain range, pinholes may occur. , short circuits between wires, etc. occur, resulting in serious failures in the functionality of the semiconductor device.
それで、金属突起電極等の膜厚を測定し、半導体装置の
信頼性向上を図っており、かかる膜厚の測定は、表面グ
ロファイラーを使用し、金属突起電極等の物理的段差を
機械的に測定し、その膜厚の許価をしていた。Therefore, we are trying to improve the reliability of semiconductor devices by measuring the film thickness of metal protruding electrodes, etc. To measure the film thickness, we use a surface grof filer to mechanically measure the physical level difference of metal protruding electrodes, etc. Measure and make allowances for its film thickness.
(発明が解決しよう゛とする問題点)
しかしながら、従来の膜厚測定法では、金属突起電極等
の物理的段差を機械的に測定していたので、測定に多く
の工程を要し、長時間を要するうえ、機械的接触により
金属突起電極等の表面に傷が付きやすいという問題点が
あった。(Problems to be solved by the invention) However, in the conventional film thickness measurement method, physical steps such as metal protrusion electrodes were mechanically measured, which required many steps and a long process. There are problems in that it takes time and the surface of the metal protruding electrodes etc. is easily damaged due to mechanical contact.
(問題点を解決するための手段)
本発明は上記従来技術の問題点に鑑み、導体鍍膜の成長
時に、各々の鍍成長開始点間の間隔が導体Ndの許容最
大値の2倍である第1モニタ対と、各々の鍍成長開始点
間の間隔が導体鍍膜の許容最小値の2倍である第2モニ
タ対とを少くとも設けたことを要旨とする。(Means for Solving the Problems) In view of the above-mentioned problems of the prior art, the present invention provides a method in which, when growing a conductor film, the distance between each film growth start point is twice the maximum allowable value of the conductor Nd. The gist is that at least one pair of monitors and a second pair of monitors in which the distance between the starting points of each plate growth is twice the minimum allowable value of the conductive plate are provided.
(作用)
上記第1モニタ対と第2モニタ対との上には、導体鍍嗅
の成長時に該導体WMIが鍍成長開始点から等方的に成
長を開始し、護膜厚が許容最小値を超えると第2モニタ
対が接続し、護膜厚が許容最大値を超えると第1モ二り
対が接続する。その結果第1.第2モニタ対間にそれぞ
れ電流の流れないとき、および第1.第2モニタ対間に
それぞれ1を流の流れるときは、いずれも護膜厚が許容
範囲外になシ、第1モニタ対間には電流が流れないが、
第2モニタ対に電流が流れるときのみ護膜厚が許容範囲
内にあることを知ることができる。(Function) On the first pair of monitors and the second pair of monitors, the conductor WMI starts to grow isotropically from the starting point of the ridge growth when the conductor ridge grows, and the protective film thickness reaches the minimum allowable value. When the protective film thickness exceeds the maximum allowable value, the second monitor pair connects, and when the protective film thickness exceeds the maximum allowable value, the first monitor pair connects. As a result, 1. When no current flows between the second pair of monitors, and when no current flows between the second pair of monitors, and the first pair of monitors. When a current flows between the second pair of monitors, the protective film thickness is not within the allowable range, and no current flows between the first pair of monitors.
Only when current flows through the second pair of monitors can it be known that the coating thickness is within an acceptable range.
(実施例)
第1図乃至第8図は本発明の一実施例を示す図であり、
図中1は、すでに累子の形成さ扛た半導体基板を示して
おり、該基板1上には、白金の第1モニタ対2と白金の
第2モニタ対3とが全突起電極4と共にパターン形成さ
nている。第1モニタ対2と第2モニタ対3とは、抵抗
体5で接続されており、第1モニタ対2と全突起成極4
とはアルミ配線6で接続されている。(Example) FIGS. 1 to 8 are diagrams showing an example of the present invention,
Reference numeral 1 in the figure shows a semiconductor substrate on which a resistor has already been formed. On the substrate 1, a first pair of platinum monitors 2 and a second pair of platinum monitors 3 are patterned together with all protruding electrodes 4. It is formed. The first monitor pair 2 and the second monitor pair 3 are connected by a resistor 5, and the first monitor pair 2 and the entire protrusion polarization 4
It is connected with aluminum wiring 6.
続いて、一実施例の製造工程を説明すれば、半導体基板
1上に金属薄膜を被着した後、エツチング法、又はり7
トオフ法で第1.第2モニタ対2゜3、および全突起電
極4を形成し、抵抗体5はリングラフィ工程と拡散工程
とで、ポリシリコンに不純物を導入して得る。また、ア
ルミ配線6もアルミ膜を被着した後、これをリングラフ
ィ工程でパターン形成して得る。Next, to explain the manufacturing process of one embodiment, after a metal thin film is deposited on the semiconductor substrate 1, an etching method or an etching method is used.
The first method using the Tooff method. A second monitor pair 2.3 and all protruding electrodes 4 are formed, and a resistor 5 is obtained by introducing impurities into polysilicon using a phosphorography process and a diffusion process. Further, the aluminum wiring 6 is also obtained by depositing an aluminum film and then forming a pattern using a phosphorography process.
かようにして第1図および第2図で示された溝造を得た
後、半導体基板1.第1.第2モニタ対2.3および全
突起電極4等上にホトレジスト7を塗布し、これをパタ
ーン形成して略正方形の孔8.9.10を第1.第一2
モニタ対2,3および電極4上にそれぞれ穿設する(第
3.第4図)。孔8は互に1辺が平行な正方形であるの
で、各々の対角線の交点が鍍成長開始点11であり、孔
9も同様に各々の対角線の交点が鍍成長開始点12にな
る。鍍成長開始点11の間隔は護膜の膜厚許容最大値の
2倍であり、鍍成長開始点12の間隔は膜厚許容最小値
の2倍である。After obtaining the groove structure shown in FIGS. 1 and 2 in this manner, the semiconductor substrate 1. 1st. A photoresist 7 is applied on the second monitor pair 2.3 and all the protruding electrodes 4, etc., and is patterned to form approximately square holes 8.9.10 on the first. 12th
Drills are made on the monitor pair 2, 3 and the electrode 4, respectively (FIGS. 3 and 4). Since the hole 8 is a square with one side parallel to each other, the intersection of each diagonal line is the sill growth starting point 11, and similarly for the hole 9, the intersection of each diagonal line is the sill growth starting point 12. The interval between the ridge growth starting points 11 is twice the maximum allowable thickness of the protective film, and the interval between the ridge growth starting points 12 is twice the allowable minimum thickness of the protective film.
しかる後、半導体基板1は金鍍敢に浸漬され、基板1と
陽極電極板との間に通電し、鍍工程を行なう。その結果
、孔8〜10内から破膜が成長し、護膜がホトレジスト
7の膜厚を超えると、護膜は鍍成長開始点11.12を
中心として等方的に成長する。所定時間の鍍工程が終K
L、ホトレジスト7が除去されると、第1.第2モニタ
対2,3および’ICIC上には、略傘状の金矢起12
,13,14がそれぞれ形成されている(第5図、第6
図)。Thereafter, the semiconductor substrate 1 is immersed in gold plating, and electricity is applied between the substrate 1 and the anode electrode plate to perform the plating process. As a result, a broken membrane grows from within the holes 8 to 10, and when the protective membrane exceeds the film thickness of the photoresist 7, the protective membrane grows isotropically around the ridge growth starting point 11, 12. The plating process for the specified time is completed.
L. When the photoresist 7 is removed, the first.L. On the second monitor pair 2, 3 and 'ICIC, there is a roughly umbrella-shaped gold arrow 12.
, 13, and 14 are formed respectively (Fig. 5, 6).
figure).
続いて、叡工程で成長した金破膜の膜厚測定法を説明す
る。測定に際しては、全突起電極4間に所定電圧を印加
する。まず、膜厚が許容範囲内なら、第2モニタ対2上
の全突起13は、鍍工程中の等方成長により第5図およ
び第6図に示す如く互に接続されているので、電極4間
には抵抗体5による電圧降下が測定される。こnに対し
、膜厚が許容最小値未満なら全突起12.13はいずれ
も接続していないので、電極4間は通電しない。Next, a method for measuring the thickness of the broken gold film grown in the process will be explained. During the measurement, a predetermined voltage is applied between all the protruding electrodes 4. First, if the film thickness is within the allowable range, all the protrusions 13 on the second monitor pair 2 are connected to each other as shown in FIGS. In between, the voltage drop across the resistor 5 is measured. On the other hand, if the film thickness is less than the minimum allowable value, none of the protrusions 12, 13 are connected, and therefore no current flows between the electrodes 4.
一方、膜厚が許容最大値を超えていると、全突起13も
接続するので、第1モニタ対2が短絡し、電極4間の電
圧降下は減少する。よって、電極4間の電圧を測定する
ことKより、膜厚が許容範囲内か否かを判別することが
できる。On the other hand, if the film thickness exceeds the maximum allowable value, all the protrusions 13 are also connected, so the first monitor pair 2 is short-circuited and the voltage drop between the electrodes 4 is reduced. Therefore, by measuring the voltage between the electrodes 4, it is possible to determine whether the film thickness is within the allowable range.
加えて、上記一実施例では、第1モニタ対2を全突起電
極4に接続し、を極4を膜厚判別時の電極と兼用しだの
で、半導体装置の検量工程で自動的に護膜厚の判別もな
され、検査工程の減少を図ることができる。In addition, in the above embodiment, the first monitor pair 2 is connected to the full-projection electrode 4, and the electrode 4 is also used as an electrode for film thickness determination, so that the protective film is automatically detected during the calibration process of the semiconductor device. Thickness is also determined, and the number of inspection steps can be reduced.
さらにモニタ対を゛三対以上設け、鍍成長開始点間距離
を多段階に変化させれば、精密な膜厚の測定も行なえる
。Furthermore, if three or more pairs of monitors are provided and the distance between the ridge growth starting points is varied in multiple stages, precise film thickness measurements can be performed.
(効果)
以上説明したように、本発明では、鍍成長開始中心間距
離が護膜厚の許容最大値の2倍である第1モニタ対と、
鍍成長開始点間距離が護膜厚の許容最小値の2倍である
第2モニタ対とを少くとも有するようにしたので、各モ
ニタ対間の導通の有無で膜厚を検査することができ、導
体護膜に易を付けることなく、かつ、簡単に膜厚の検査
ができるという効果を有する。(Effects) As explained above, in the present invention, the first pair of monitors in which the distance between the centers of ridge growth initiation is twice the maximum allowable value of the protective film thickness;
Since there is at least a second pair of monitors in which the distance between the starting points of the ridge growth is twice the minimum allowable value of the protective film thickness, the film thickness can be inspected by checking the presence or absence of conduction between each pair of monitors. This has the effect that the film thickness can be easily inspected without damaging the conductor protective film.
第1図は不発明の一実施例を示す平面図、第2図fa)
乃至(C)は第1図のA−A’乃至c−c’断面図、第
3図は一実施例の途中工程を示す平面図、第4図(a)
乃至(C)は第3図の第2図(a)乃至(C)と同位置
における断面図、第5図は膜厚が許容範囲内にある場合
の一実施例を示す平面図、第6図(a)乃至(C)は第
5図の第2図(a)乃至(C)と同位置くおける断面図
、第7図は膜厚が許容最大値を超えた場合の一実施例を
示す平面図、第8図(a)乃至fe)は第7図の第2図
(a)乃至(C)と同位置における断面図である。
1・・−・・・基板、2・・・・・−第1モニタ対、3
・・・・・・第2モニタ対、11.12・−・・・・鍍
成長開始点、14・・・・・・導体護膜。
代理人 弁理士 内 原 晋 ゛込1五 1図
策 2図
筋3回 筋4図
荒S図 筋乙回
粥7目 筋8回Fig. 1 is a plan view showing an embodiment of the invention, Fig. 2 fa)
1. FIG. 3 is a plan view showing an intermediate step in one embodiment. FIG. 4(a)
3. FIG. 5 is a plan view showing an example when the film thickness is within the allowable range. Figures (a) to (C) are cross-sectional views taken at the same positions as Figures 2 (a) to (C) in Figure 5, and Figure 7 shows an example in which the film thickness exceeds the maximum allowable value. The plan view and FIGS. 8(a) to fe) are cross-sectional views taken at the same positions as FIGS. 2(a) to (C) in FIG. 7. 1...-board, 2...-first monitor pair, 3
. . . 2nd monitor pair, 11. 12 . . . ridge growth starting point, 14 . Agent Patent Attorney Susumu Uchihara ゛Includes 15 1 drawing plan 2 drawing plot 3 plots plot 4 plot rough S plot plot 7th plot plot 8 plots
Claims (1)
モニタパターンにして、該モニタパターンは、少くとも
、各々の鍍成長開始点間の間隔が導体鍍膜の許容最大値
の2倍である第1モニタ対と、各々の鍍成長開始点間の
間隔が導体鍍膜の許容最小値の2倍である第2モニタ対
とを有しており、第1モニタ対と第2モニタ対上には導
体鍍膜成長時に導体鍍膜が成長可能である鍍膜厚測定用
モニタパターン。A monitor pattern for measuring the thickness of a conductive coating grown isotropically on a substrate, the monitor pattern having a distance between each coating growth starting point that is at least twice the maximum allowable value of the conductive coating. a first pair of monitors and a second pair of monitors in which the spacing between the starting points of each coating is twice the minimum allowable value for the conductive coating; is a monitor pattern for measuring the thickness of the conductive film that can be grown during the growth of the conductive film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22440985A JPS6282305A (en) | 1985-10-07 | 1985-10-07 | Monitor pattern for measurint thickness of plating film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22440985A JPS6282305A (en) | 1985-10-07 | 1985-10-07 | Monitor pattern for measurint thickness of plating film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6282305A true JPS6282305A (en) | 1987-04-15 |
Family
ID=16813311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22440985A Pending JPS6282305A (en) | 1985-10-07 | 1985-10-07 | Monitor pattern for measurint thickness of plating film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6282305A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03273635A (en) * | 1990-03-23 | 1991-12-04 | Fuji Electric Co Ltd | Semiconductor device provided with bump electrode |
US10487685B2 (en) | 2015-02-03 | 2019-11-26 | Mitsubishi Hitachi Power Systems, Ltd. | Piping system cleaning method, piping system, and steam turbine plant |
-
1985
- 1985-10-07 JP JP22440985A patent/JPS6282305A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03273635A (en) * | 1990-03-23 | 1991-12-04 | Fuji Electric Co Ltd | Semiconductor device provided with bump electrode |
US10487685B2 (en) | 2015-02-03 | 2019-11-26 | Mitsubishi Hitachi Power Systems, Ltd. | Piping system cleaning method, piping system, and steam turbine plant |
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