JPS6281982A - Generation system of pwm signal - Google Patents

Abstract

PURPOSE:To generate a stable modulation signal in the whole region having constant modulation frequency by preventing the change of the direction of counting of a counter outputting the address of the modulation signal at the time of the rotation and changeover of the phase of an output from an inverter. CONSTITUTION:A frequency command is inputted to a function generator 7, and an output from the function generator 7 is converted into clock pulses by a V/F converter 8. The clock pulses are changed into a phase signal by a counter 9, and added to an output from a counter 2 by an adder 10 and turned into the address of a ROM4. Data corresponding to a sine-wave one period are written to a ROM3 as a reference signal and data corresponding to a triangular-wave twelve period to the ROM4 as a modulation signal respectively, and these data are compared by a comparator 6 and a PWM signal is outputted. An output from a polarity discriminating circuit 11 is introduced only to the counter 2, thus changing only the direction of counting of the counter 2 at the time of the changeover of forward or reverse rotation, then inverting the phase rotation of the reference signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse width modulation (PWM) signal generation method in a variable voltage/variable frequency inverter.

[Conventional technology]

The PWM pulse calculation or generation method is shown in Figure 3 (
As shown in (a), a method for generating PWM pulses as shown in (b) of the same figure is known by comparing the magnitudes of the sine wave S, which is the inverter output voltage reference signal, and the triangular wave T, which is the modulation signal. It is being In this case, if the frequency of the triangular wave is sufficiently higher than the frequency of the sine wave, low-order harmonics included in the calculated pwM waveform are removed. However, since the frequency of the triangular wave is related to the switching frequency of the inverter, the upper limit frequency of the triangular wave is limited due to the characteristics of the semiconductor elements used in the inverter, the characteristics of the commutation circuit and gate drive circuit, or the inverter loss. Ru.

Here, the frequency of the triangular wave is fc, the frequency of the sine wave is f,
, the ratio r c /f + is defined as the modulation ratio n. Since the upper limit value of the modulation frequency (fc, ax) is limited, the inverter frequency (sine wave frequency t2!,) r+
As the value of n increases, the value of n must be decreased. In this case, if n<10 and the sine wave and triangular wave are not synchronized, the calculated PWM waveform will include low-order harmonics, which may cause beats in the inverter output voltage and current. . For this reason, when n is not high enough, it is common practice to synchronize the sine wave and the triangular wave. Furthermore, in order to reduce current ripple by increasing the modulation ratio and modulation frequency as much as possible for each inverter frequency, the relationship between f and fl is controlled as shown in Figure 4. ing.

An example of a configuration for realizing the above is shown in FIG.

Here, the inverter frequency command f1' is converted by a voltage/frequency (V/F) converter 1 into a clock pulse flcL proportional to the inverter frequency f1.

The clock pulse flcL is input to an up/down counter 2 and counts up to a predetermined number k. Figure 6 (a) shows the output θ of this counter.
and this θ1 is the sine wave ROM3. Triangle wave ROM
This address is used as address 4. In ROM3.4, for example, FIG. 6 (b) is stored.

Patterns of a sine wave S and a triangular wave T as shown in (c) are respectively written. In addition, FIG. 6 shows the modulation ratio n
=3 is shown. A triangular wave pattern is written in the ROM 4 for each modulation ratio, and the waveform is selected to have the characteristics shown in Figure 4 using the frequency command r° and the voltage magnitude command value ■1. Ru. On the other hand, ROM3
Since the output of is a unit sine wave, the output of the ROM 3 is multiplied by ■1 in order to use this as a voltage command. Although FIG. 5 shows an example in which the digital multiplier 3 is used, instead of this, the output of the ROM 3 may be D/A converted and then analog multiplied. The output of the multiplier 5 and the output of the ROM 4 are compared in magnitude by a comparator 6, thereby forming a PWM pulse as shown in FIG. 3(b). In addition, up/down counter 2 and ROM 3.4
The output of is a digital quantity, but for convenience it will be considered as an analog quantity.

However, according to this method, as shown in FIG. 6, the data of the sine wave and the triangular wave are accessed by the same address θ1, so they are completely synchronized. However, determining the address that indicates one period of the sine wave determines the phase resolution, and while there is no problem when the number of triangular waves written in the same one period is small (the modulation ratio is small), when the modulation ratio is increased, the phase resolution is determined. The resolution is poor, making it impossible to write triangular waves. In order to increase the modulation ratio, the phase resolution must be increased, which increases the number of addresses per cycle, resulting in an increase in ROM capacity. Furthermore, when one period of the sine wave is written to Q- up to the address, r+ct=kf, so as k increases, flcL becomes extremely large. For example, k=4
096 and the inverter is operated up to 10011z, the frequency is as high as f+cL=409, 6 KHz, and it is not easy to oscillate such a high frequency accurately.

On the other hand, if the maximum frequency of flcL is limited using a ROM with limited capacity, the maximum modulation ratio is determined, so as the inverter frequency decreases, the frequency of the triangular wave must also decrease, resulting in current ripple at low speeds. Problems arise such as poor response due to low angular resolution and low angular resolution.

Therefore, the applicant has proposed a system as shown in FIG. 7 (Japanese Patent Application No. 61,892/1989; hereinafter referred to as the system for which the application has been filed).

This is constructed by adding a portion surrounded by a chain line to the one shown in FIG. 5. The chain line portion in FIG. 7 is composed of a function generator 7, a voltage/frequency (V/F) converter 8, an amplifier down counter 9, an adder 10, a polarity discrimination circuit 11, and the like.

A frequency command f is input to the function generator 7, and its output r is converted by the V/F converter 8 into a clock pulse having a frequency fTCL. f TCL is converted into a phase signal θ7 by a counter 9, and further added to θ1 by an adder 10 to obtain θ, which (0, 4) is used as the address of the ROM 4 in which the modulation signal is written. This
For example, ROM3 stores data for one period of a sine wave as a reference signal, and ROM4 stores data for one cycle of a triangular wave as a modulation signal.
Assuming that two cycles of data are written respectively, the waveform data at this time is shown in analog form as shown in FIG. When the reference signal and the modulation signal are operating in synchronization, the up/down counter 9 is reset by the signal S3 so that θT=O. As a result, θ8=θ, resulting in operation with a modulation ratio n=12.

FIG. 9 shows the relationship between the reference signal frequency f1 and the modulation signal frequency f. Now, the maximum modulation frequency is f C (mmx)
If the maximum reference frequency that can be operated at n-12 is flm, then the relationship f C (IIIX) = 12 f + a holds true. In other words, the reference frequency is from fo to f
0 is a synchronous operation state, and as the reference frequency decreases, the modulation frequency also decreases. If it is assumed that the operation shifts to a constant modulation frequency when the reference frequency becomes smaller than fIb, the final modulation frequency during synchronous operation will be 12f+b.

Therefore, in order to set the modulation frequency to f C (saw), the frequency must be increased by 12 (fl-fib). That is, when operating at an inverter frequency f1 that is lower than r0, it is necessary to add only 12 (ft, -fl) frequencies, and the portion where this frequency is added is the dot-dashed line in FIG. At this time, R.O.
Since a modulation signal with a modulation ratio n is written in M4, its frequency fC is f(=n (f, ” +fT)=n
r.

becomes. Therefore, it can be seen that the function generator 7 shown in FIG. 7 may be configured to satisfy the relationship shown in FIG. 10. In this case, lr+"l, which is the absolute value of the command f1', is input to the function generator 7.

[Problem to be Solved by the Invention 3] In the above PWM signal generation system, in order to reverse the inverter during asynchronous operation (constant modulation frequency operation), θ1. The phase rotation of θ4 may be reversed. That is, the polarity of the inverter frequency command f1'' is determined by the polarity determination circuit 11, and the up/down counter 2 is determined accordingly.
．． All you have to do is change the days when you count up or down in the direction of the count of 9. However, in such a case, if the command f1' contains a ripple, the polarity discrimination circuit 11 repeatedly outputs positive and reverse signals in the vicinity of f-S0, so the counting direction of the counters 2 and 9 changes repeatedly. I will do it. Since the counter 9 is generating a modulation signal, when the positive and reverse signals change rapidly, θ
If the number 7 changes to a positive value or a negative value, and the absolute values of both are equal, there will be a case where the number 8 does not change on average, and the phase may not advance. In this case, there is a problem that operation with a constant modulation frequency can no longer be continued and voltage control ability is lost. To deal with this, it may be possible to provide a filter to reduce the flm ripple or to widen the hysteresis width of the polarity determining circuit, but if this is done, a problem arises in that the frequency response is significantly lowered.

Therefore, an object of the present invention is to provide a PWM signal generation method that can keep the modulation frequency constant even when the inverter frequency command is near zero when generating a PWM signal based on the inverter frequency command.

[Means for solving problems]

a first memory (ROM) that stores reference signal data; a second memory (ROM) that stores modulated signal data; A first phase signal generating means for reading data from the second memory, a second phase signal generating means having a predetermined relationship with the first phase, and a second phase signal generating means for adding the first phase and the second phase. and a third phase signal generating means for reading data from the second memory.

[Effect]

By comparing the magnitude of the output voltage reference signal and the modulation signal, P
In a device that calculates WM pulses, a ROM in which an output voltage reference signal and a modulation signal are written in advance is accessed by associating the voltage phase with an address, and the reference signal and modulation signal are synchronized and operated (synchronized). When driving),
While operating both ROMs using the same address,
When the inverter frequency decreases, an address dependent on the frequency command is added to the address of the ROM where the modulation signal is written, thereby performing asynchronous operation to keep the frequency of the modulation signal constant. When reversing the phase rotation of the inverter output, the phase rotation of only the first phase signal is reversed, and the phase rotation of the third phase signal is not changed.

〔Example〕

FIG. 1 is a configuration diagram showing an embodiment of this invention, and FIG.
3 is a graph showing the characteristics of the function generator used in the figure.

That is, this embodiment is characterized in that the output of the polarity determining circuit 11 is introduced only into the amplifier down counter 2, and that a function generator 7' having characteristics as shown in FIG. 2 is provided.

By doing this, when switching between forward and reverse, the counter 2
Only the counting direction of is changed, and the phase rotation of the reference signal is reversed. On the other hand, since it is necessary to keep the frequency of the modulation signal constant, the function generator 7' is provided with characteristics as shown in FIG. Now, when the rotation is in the normal direction, f-〉0, and f +"= I fl" l, then in the normal rotation, 6 is as shown in Fig. 10.
The modulation frequency fC becomes f,=n (fdotenft) =nfIm, and a constant modulation frequency is output even if the reference frequency is zero, while in the case of inversion, fT=-f, etc. +fla becomes f,"+f,=f-+ (-f,")+f,.

=fl! So, the modulation frequency fc is f,=nf,.

Therefore, it will be kept constant. As a result, the phase rotation of only the reference signal is reversed, and the modulation signal is output without phase rotation, so that it is possible to perform good control of zero frequency and zero voltage.

〔Effect of the invention〕

This invention has the advantage that it is possible to generate a stable modulation signal over the entire range where the modulation frequency is constant, since the counting direction of the counter that outputs the address of the modulation signal is not changed when switching the phase rotation of the inverter output. is brought about.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a graph showing the characteristics of the function generator used in this invention, and FIG.
The figure is a reference diagram for explaining the waveforms of the standard output signal, modulation signal, and PWM signal. Figure 4 is a graph showing the relationship between the inverter frequency and modulation signal frequency. Figure 5 is the PWM signal.
A block diagram showing a conventional example of the signal generation method, FIG. 6 is a waveform diagram of each part to explain the operation of FIG. 5, FIG. 7 is a block diagram showing a method for which an application has been filed, and FIG. A reference diagram showing examples of data stored in the sine wave ROM and triangular wave ROM in analog waveforms, Figure 9 is a graph showing the relationship between the reference signal frequency and modulation signal frequency, and Figure 10 is the function in Figure 7. It is a graph showing the characteristics of the generator. Code explanation 1.8...Voltage/frequency (V/F) converter, 2゜9・
...Up-down counter, 3...ROM for sine wave,
4... ROM for triangular wave, 5... Multiplier, 6... Comparator, 7, 7'... Function generator, 10... Adder, 11... Polarity discrimination circuit. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzakigaaa No. 511!1 1i61111! 17Ill Ills diagram

Claims (1)

[Claims] a first memory that stores waveform data for one cycle of an output reference signal in order to generate a pulse width modulation (PWM) signal to be applied to each switching element constituting the inverter main circuit;
a second memory for storing waveform data for a predetermined period of a modulated signal; a first phase signal generating means for generating a first phase signal for reading data from the first and second memories; a second phase signal generating means for generating a second phase signal having a predetermined relationship with the first phase signal;
a third phase signal generating means for generating a third phase signal for reading data from the second memory by adding the phase signal to the second memory; 1. Synchronize the reference signal and the modulation signal by supplying it to the second memory to generate a PWM signal, and enable the second phase signal to supply the first phase signal to the first memory and the second memory to the second memory. A PWM signal generation method that generates a PWM signal by desynchronizing a reference signal and a modulation signal by applying a third phase signal, and reverses the phase rotation of an inverter output when the reference signal and modulation signal are out of synchronization. A PWM signal characterized in that the phase rotation of only the first phase signal is reversed and the phase rotation of the third phase signal is not changed, thereby stably outputting the modulated signal in the entire frequency range including near zero frequency. How it occurs.