JPS6281766A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the number of information rewriting times, by specifying the minimum value of the thickness of an silicon oxide film at a slant part in the transition region of a gate silicon oxide film, which is provided with two kinds of film thicknesses, so that the value is sufficiently larger than the thickness of a gate silicon oxide film of an insulating-gate type, field-effect, nonvolatile, memory transistor. CONSTITUTION:On an N-type silicon substrate 3, a P<+> type conductor layer 2 and a silicon oxide film 1 are formed. Then a hole is provided in the silicon oxide film 1. A P-type low concentration layer 4 is formed in the gate region. Thereafter, a gate silicon oxide film 8 is formed. A hole is selectively formed in a region, which is to become the gate of an insulating-gate type, field-effect, nonvolatile, memory transistor 31 by using photoresist 5. The silicon oxide film in the region, where the hole is provided, is removed to the surface of the silicon substrate by a directional etching method. Then, a gate silicon oxide film 9 of the insulating-gate type, field-effect, nonvolatile memory transistor is formed by a thermal oxidation method by 20Angstrom . Then, a silicon nitride film 6 is deposited, contact holes are selectively provided in the silicon substrate 3 and the P<+> type conductor layer 2 and thus, a metal electrode 7 is formed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device, particularly a so-called tri-gate structure semiconductor memory device comprising an insulated gate field effect transistor and an insulated gate field effect nonvolatile memory transistor. It is about improvement.

[Conventional technology]

Conventionally, when this type of nonvolatile semiconductor memory device is arranged in a matrix pattern on a single semiconductor substrate, an insulated gate field effect nonvolatile memory transistor is normally on (Φ).
In order to prevent bit selection from becoming impossible (normally-on) when reading memory data, a normally-off (normally-on) transistor is connected in series to each memory transistor.
A commonly used method is to connect insulated gate field effect transistors with a fixed gate threshold voltage (normally-off).

As a practical example, a so-called tri-gate structure or dual-gate structure semiconductor memory device is used, which includes an insulated gate field effect transistor and an insulated gate field effect nonvolatile memory transistor.

Unfortunately, the insulated gate field-effect non-destructive memory transistor used there often uses a two-layer insulating film structure called MNOS.

The so-called tri-gate structure conventionally used, as shown in FIG. 3, usually uses an n-substrate 53, and the insulated gate "1 field effect transistor section 90 has a silicon oxide film 93 with a thickness of 2000 to 3000 Å. Silicon oxide film thickness 9 of thick, insulated gate field effect nonvolatile memory transistor section 91
The thickness of the silicon oxide film 4 is formed to be as thin as 20 to 40 Å, and at the boundary between the different film thicknesses, a sloped portion 92 of the gate i-oxide film is formed, where the thickness of the silicon oxide film gradually changes.

In addition, both of them have a common silicon nitride film 56 of 400~
It is formed to have a thickness of 800 Å, and a gate electrode 57 is formed thereon. Note that 51 is a silicon oxide film, and 52 is a p
It is a + type conductive layer.

[Problem that the invention seeks to solve]

As shown in FIG. 3, the semiconductor memory device using the above-mentioned conventional tri-gate structure has the thickness of the gate oxide film 93 of the insulated gate field effect transistor 90 and the gate oxide film 94 of the insulated gate field effect nonvolatile memory transistor 91.
The thickness of the silicon oxide film gradually changes from 20 to 40A to 2000 to 3000A at the boundary between the two. A sloped part 92 of the membrane is formed, and in this part,
Complete writing and erasing are not performed, and charges accumulated in the gate silicon oxide film, which is relatively thicker than the gate oxide film of the insulated gate field effect nonvolatile memory transistor 91, which is 20 to 40A thick, are erased during erasing. (In other words, a state in which charges are returned to the silicon substrate from the interface of the two-layer gate insulating film) Writing is performed for the second and third time (charges are injected from the silicon surface to the interface of the two-layer gate insulating film) without being completely returned to the silicon surface. The charge left behind during erasing is sequentially injected into the gate silicon oxide film in the thick direction by the electric field applied to the gate during subsequent writing. The gate electric field applied to the silicon oxide film becomes smaller in the direction of the thickness of the silicon oxide film, and finally,
Even if an erase operation is performed, it becomes impossible to return to the initial threshold voltage (a state in which there is no charge at the interface of the two-layer gate insulating film), and the number of alarm erases of the memory contents, that is, the number of rewrites, becomes extremely large. There were disadvantageous drawbacks in reducing the amount of water and increasing the number of soda changes.

Conventionally, in order to avoid the above-mentioned drawbacks, as shown in FIG. substrate·
By providing a deep diffusion layer 80 of opposite conductivity type,
The idea was to eliminate fluctuations in threshold voltage due to charges left behind during erasing injected into the sloped portion of the gate oxide film, thereby increasing the number of times information can be rewritten.

However, in the conventional method, a diffusion layer is provided in the sloped part of the gate oxide film, which increases the area occupied by the memory transistor cell, making it difficult to improve the degree of integration of semiconductor memory devices, which is an issue for the future. It has a major drawback in that it is disadvantageous for increasing capacity, high integration, and high speed.

The present invention improves the drawbacks of the conventional so-called tri-gate structure described above and increases the number of times information can be rewritten, while at the same time increasing memory capacity and achieving high integration.

An object of the present invention is to provide a semiconductor memory device that can achieve high speed.

[Means for solving problems]

The semiconductor memory device of the present invention includes an insulated gate field effect transistor with different gate silicon oxide film thickness and an insulated gate field effect transistor with different gate silicon oxide film thicknesses.
In a so-called tri-gate structure semiconductor memory device having a field-effect nonvolatile memory transistor, a gate insulating film thickness transition region of the insulated gate field-effect ball extrusion memory transistor portion and the insulated gate field-effect transistor portion is provided. The structure has a structure in which the minimum value of the silicon oxide film thickness of the sloped portion is formed to be sufficiently thicker than the gate silicon oxide film thickness of the insulated gate field effect nonvolatile memory transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1-fd) are longitudinal cross-sectional views shown in order of steps to explain the first embodiment of the present invention and its manufacturing method.

First, as shown in FIG. 1(a), an n-type silicon substrate 3
A p-type conductive layer 2 is selectively formed thereon by a thermal diffusion method using a photolithography technique, and then a silicon oxide film 1 of 6000 Å is formed by a thermal oxidation method.

Next, as shown in FIG. 1(b), the silicon oxide film in the gate region of the insulated gate field effect transistor and the insulated gate field effect nonvolatile memory transistor is selectively opened using photolithography. A p-type low concentration layer 4 is formed by ion implantation. Next, the gate silicon oxide film 8 of the insulated gate field effect transistor is formed by thermal oxidation! 1) Form 2500A. Thereafter, a photoresist 5 is used to selectively open the region that will become the gate of an insulated gate field effect nonvolatile memory transistor in the future, and the silicon oxide film in the open region is directionally etched (physically etched). The surface of the silicon substrate 3 is also removed.

Next, as shown in FIG. 1(c), a gate silicon oxide film 9 of an insulated gate field effect nonvolatile memory transistor is formed by a 20A thermal oxidation method.

Next, as shown in FIG. 1fd), a silicon nitride film 6 is deposited for 600'A by low pressure CVD, and then contact holes to the silicon substrate 3 and the p-type conductive layer 2 are selectively formed by photolithography. opening and metal electrode 7 at 1
．． A semiconductor memory device is completed by forming by a 2 μm sputtering method.

FIG. 2 (at to +d) is a longitudinal cross-sectional view shown in order of steps to explain a second embodiment of the present invention and its manufacturing method.

First, as shown in FIG. 2(a), an n-type silicon substrate 1
A p+ type conductive layer 12 is selectively formed on the photolithography layer 3 by a thermal diffusion method, and then a silicon oxide film 11 of 6000 Å is formed by a thermal oxidation method.

Next, as shown in FIG. A p-type low concentration layer 14 is formed by ion implantation, and a gate silicon oxide film 18 of 2500 A is formed by thermal oxidation on the insulated gate' and field effect transistor.Thereafter, a future insulated gate field effect nonvolatile memory transistor is formed. A photoresistor 15 is used to selectively open a region that will become a gate, and the silicon oxide film in the opened region is etched by about 1500 Å from the surface of the silicon oxide film using an isotropic etching (chemical etching) method. after that,
Subsequently, by directional etching (physical etching), the silicon oxide film thickness slope portion 42 on the silicon substrate 13 is etched to a minimum thickness of too much by removing the silicon oxide film up to the surface of the silicon substrate 130.

A and the gate oxide film thickness 19 of the field effect nonvolatile memory transistor, which is 20A, are formed to be sufficiently thick.

Next, as shown in FIG. 2(c), a gate silicon oxide film 19 of an insulated gate field effect nonvolatile memory transistor is formed by thermal oxidation.

Thereafter, as shown in FIG. 2(d), a silicon nitride film 16 is deposited on a 600A film 11 by low-pressure CVD, and then a silicon substrate 13 and a film are deposited by photolithography.
A contact hole in the green conductive layer 12 is selectively opened, and a metal electrode 17 is formed by sputtering to a thickness of 12 μm.
A semiconductor memory device according to the embodiment is completed.

In explaining the present invention in detail above, the field effect
``I: Although a tri-gate structure has been described in which two field-effect transistors are used for one field-effect nonvolatile memory transistor, the present invention provides an electric field for one field-effect nonvolatile memory transistor. The present invention can also be applied to a so-called dual gate structure composed of one effect transistor.

〔Effect of the invention〕

As explained above, the present invention provides that the minimum value of the silicon oxide film thickness of the slope part in the transition region of the gate silicon oxide film with two types of film thickness is the gate silicon oxide film of an insulated gate field effect nonvolatile memory transistor. By forming the film to be sufficiently thicker than the film thickness, no charge injection into the sloped portion of the gate insulating film that occurs when writing or erasing information in the memory transistor will occur, and no charge will be left behind during erasing operations. (The number of rewrites of the H signal is further improved from the conventional °10S times to 106 to 107 times, and a fully satisfactory function of electrically rewriting is easily realized. Also, the slope of the gate silicon oxide film There is no need to provide a diffusion layer to increase the number of rewrites,
The area occupied by the memory transistor cell is 25 to 3
Since the chip is smaller, high integration is possible, and at the same time,
High-speed operation is also possible, and the effect is that increasing memory capacity, which is a future technical issue, can be easily achieved.

Furthermore, when removing the silicon oxide film from the gate region of an insulated gate field-effect nonvolatile memory transistor, a directional etching (physical etching) method is used, so if the etching conditions are considered, the silicon oxide film in the gate region Since minute protrusions can be easily formed on the substrate, the information rewriting voltage can be lowered, and low-voltage operation can be realized.

[Brief explanation of drawings]

FIGS. 1(a) to fd) and FIGS. 2fa) to (d) are the first embodiment of the present invention. In order to explain the second embodiment and its manufacturing method, vertical cross-sectional views shown in the order of steps, FIGS. 3 and 4 are vertical cross-sectional views of a conventional semiconductor memory device. 2.13,52,72.80...P-type conductive layer, 3,13,53,73''-n-type silicon substrate, 1,11゜51.71...Silicon M PI
A, 5, 15... Photoresist, 4, 14
, 54.74...p-type low concentration layer, 6, 16, 5
6.76...Silicon nitride film, 8°9.18,
19, 93, 94, 103, 104... Gate silicon oxide film, 7, 17, 57, 77... Metal electrode, 30, 40, 90, 100... Insulation Gate field effect transistor, 31.41.91, Lo
t... Insulated gate field effect nonvolatile memory transistor, 42.92, 102... Slanted part of gate silicon oxide film. Agent: Susumu Uchihara, patent attorney. Third evil

Claims (1)

[Claims] In a so-called tri-gate structure semiconductor memory device comprising an insulated gate field effect transistor and an insulated gate field effect nonvolatile memory transistor having different gate silicon oxide film thicknesses, the insulated gate field effect nonvolatile memory transistor portion and the insulated gate electric field The structure has a structure in which the minimum value of the silicon oxide film thickness of the slope part in the transition region of the gate insulating film thickness of the effect transistor part is formed to be sufficiently thicker than the gate silicon oxide film thickness of the insulated gate field effect nonvolatile memory transistor. A semiconductor memory device characterized by: