JPS6281741A - Package for integrated circuit - Google Patents

Package for integrated circuit

Info

Publication number
JPS6281741A
JPS6281741A JP60224242A JP22424285A JPS6281741A JP S6281741 A JPS6281741 A JP S6281741A JP 60224242 A JP60224242 A JP 60224242A JP 22424285 A JP22424285 A JP 22424285A JP S6281741 A JPS6281741 A JP S6281741A
Authority
JP
Japan
Prior art keywords
integrated circuit
chip
electrode pads
circuit chip
metal wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60224242A
Other languages
Japanese (ja)
Inventor
Koichi Hirose
幸一 廣瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP60224242A priority Critical patent/JPS6281741A/en
Publication of JPS6281741A publication Critical patent/JPS6281741A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent deterioration in characteristics, to omit necessity of collecting electrode pads only at the peripheral part of a chip and to reduce the area of the chip, by providing a bridging part, which links facing side walls as a unitary body, and providing film wirings for connecting electrode pads, which are provided in the vicinity of the center of the integrated circuit chip on the bridging part, by using metal wires. CONSTITUTION:On an integrated circuit chip 4, electrode pads 6 are provided not only at the peripheral part but also in the vicinity of the center of the chip. A bridging part 7 is provided so as to link facing side walls 2 at both sides. Film wirings 8 on the bridging part 7 and the electrode pads 6 in the vicinity of the center of the chip are connected with short metal wires. Mounting of the chip 4 and the connection of the metal wires are performed as follows: at first, the integrated circuit chip 4 is placed under the bridging part 7 of a case substrate 1 and mounted on the case substrate; and the connection with electrode pads 5 on the integrated circuit chip is performed with metal wires 9. The electrode pads 6 in the vicinity of the center of the chip and the film wirings 8 on the bridging part 7 are connected with metal wires.

Description

【発明の詳細な説明】 〔産業上の利用分封〕 本発明は、中央部に集積回路チップをマウントするため
の凹んだキャビティを有するところの、絶縁体から作ら
れているケース基体をもつ集積回路用パッケージに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Packaging] The present invention relates to an integrated circuit having a case base made of an insulating material having a recessed cavity in the center for mounting an integrated circuit chip. Regarding the package for

〔従来の技術〕[Conventional technology]

従来の集積回路用パッケージのケース基体に、集積回路
チップをマウントした状態の斜視図を第２図に示す。図
において、セラミックのケース基体１１の中央部は凹ん
だキャビティになって２９、この凹所を囲む厚い周壁１
２の上面には、凹所にマウントした集積回路チップ１４
の電極バゾド５と金属線９で接続する多数の膜配線３が
設けらｊしている。FIG. 2 shows a perspective view of an integrated circuit chip mounted on a case base of a conventional integrated circuit package. In the figure, the central part of the ceramic case base 11 is a recessed cavity 29, and a thick peripheral wall 1 surrounding this recess.
2 has an integrated circuit chip 14 mounted in a recess.
A large number of membrane wiring lines 3 are provided which are connected to the electrode baths 5 by metal wires 9.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来のケース基体でに、この基体にマウントした集
積回路チップのｔ極パッドとケース基体の膜配線との間
をつなぐ金蛎線の長さを成る可く短くするために、集積
回路チップの電極パッドをチップ周辺部に果めている。In the conventional case base mentioned above, in order to minimize the length of the wire connecting the T-pole pad of the integrated circuit chip mounted on the base and the membrane wiring of the case base, it is necessary to Electrode pads are placed around the chip.

その結果、チップ上のｔ惚パッドの占める面積が大きく
なり、当然の事ながら、チップの面積も大きくなる。ま
た、チップ中央部の累子から信号を取シ出すには、チッ
ブ周辺の１［憔パッド筐で信号線を引き回わすために、
引回しにより特性の劣化：ａｌ−もたらすという欠点が
ある。As a result, the area occupied by the pad on the chip increases, and naturally the area of the chip also increases. In addition, in order to extract signals from the central part of the chip, it is necessary to
There is a drawback that the routing causes deterioration of characteristics: Al-.

〔問題点（ｉ−解決するための手段〕[Problem (i-Means to solve)]

上ｄｄ問題点に対し５本発明では、セラミックのケース
基体の凹所にマウントした果槓回路チップの電極バッド
と金属線で接続するたりの膜自己線ｒケース基体の凹Ｉ
′ｙＴ（ｉｌ−囲ひ周壁土ｍｌＫ設ける１こけでなく、
相対向する周壁１１５　’にさし渡す橋絡部？一体に設
け、この橋絡部上にも、前記集積回路チップの中央付近
に設けた電極パッドと金属線で接続するｆｃ６Ｄの膜配
線を設けている。In order to solve the above problems, in the present invention, the film self-wire r is connected to the electrode pad of the circuit chip mounted in the recess of the ceramic case base with a metal wire.
'yT(il-enclosure surrounding wall soil mlK, not 1 moss,
A bridge section that spans the opposing peripheral walls 115'? An fc6D membrane wiring is also provided on this bridge portion, which is connected by a metal wire to an electrode pad provided near the center of the integrated circuit chip.

〔実施例〕〔Example〕

つぎに本発明を実施例に工９説明する〇第１図（ａ）は
不発明の一実施例に係るケース基体に果檀回錯ナツプ金
マウントした状態の平１図、同図（ｂ）は図（ａ）のＡ
−Ａｖｆｒ面図でるる。第１図（ａ）。Next, the present invention will be explained using an example. Figure 1 (a) is a flat view of an orchard complex napkin mounted on a case base according to an embodiment of the invention, and Figure 1 (b) is is A in figure (a)
- Avfr surface view. Figure 1(a).

（ｂＪにおいて、ケース基体１の凹所ｔ−囲む厚い周壁
２の上面には、凹所にマウントした集積回路チ。(bJ) On the top surface of the thick peripheral wall 2 surrounding the recess t of the case base 1, there is an integrated circuit chip mounted in the recess.

プ４の周辺′ＲＬ他パッド５と金属線９で接続された多
数の膜配線３が投げられている。また、集積回路チップ
４は、周辺のみならず、テラ１中央付近にも”ａｍパッ
ド６が設けらｎてお９、また、対向する両側の周壁２の
間をまたいで橋絡部７が設けられてる・ジ、この橋絡部
７上の膜配線８と、チップの中央付近の電極パッド６と
の間は、短い金属線で接続されている。A large number of film interconnections 3 connected to pads 5 and metal wires 9 are scattered around the pad 4. Further, the integrated circuit chip 4 is provided with an "am pad 6" not only at the periphery but also near the center of the terra 1, and a bridge section 7 is provided spanning between the peripheral walls 2 on both opposing sides. The film wiring 8 on the bridge portion 7 and the electrode pad 6 near the center of the chip are connected by a short metal wire.

このチップ４のマウント２よび金ｐＡ線接続はつき′の
ようにして行なわれる。すなわち、ケース基体１の橋絡
部７のドヘ集積回路テップ４’ｆ−もぐらせてケース基
体にマウントする。つき゛に、集積回路チップ上の電極
パッド５との間を金属線９で接続する。つさ゛に、チッ
プ上の中央付近の電極パッド６と、橋絡部７上の膜配線
８との間を金属線で接続するのである。The connection between the mount 2 of the chip 4 and the gold pA line is made as shown in FIG. That is, the integrated circuit tip 4'f- of the bridging portion 7 of the case base 1 is loosened and mounted on the case base. At the same time, a metal wire 9 is connected to the electrode pad 5 on the integrated circuit chip. Specifically, the electrode pad 6 near the center of the chip and the membrane wiring 8 on the bridge section 7 are connected by a metal wire.

なお上側は、橋絡部７が一個だけの例を示したが、これ
を縦横十字形に設けて接続部分の増加金図ること℃、ま
た、橋絡部上の膜配線を並行の複数本にし、接続相手の
チップ上の電極パッドの数を増加することができるのは
いうまでもない。Although the upper side shows an example in which only one bridge section 7 is provided, it is possible to increase the number of connection sections by providing it in a vertical and horizontal cross shape.Also, it is possible to increase the number of connection sections by forming multiple membrane wirings on the bridge section in parallel. Needless to say, the number of electrode pads on the chip to be connected can be increased.

〔発明の効果〕〔Effect of the invention〕

上述のように、本発明に係るケース基体では、集積回路
チップをマウントする凹所中央を−またいで相対向する
周壁間に一体の橋絡部をさし渡し、さらにこの橋絡部上
にも模配、娠を設ける。そして本発明パッケージに収容
する集積回路チップの中央付近にも電極パッドを設け、
橋絡部上の膜配線とチップ中央電極パッドとを直接金属
線で接続することによシ、チップ上の１ｇ号線の引回し
をなくすことができる。その結果、チップ上の信号線引
回しによる特性劣化が防止でさ、まだ、テッグ周辺部の
みに１１１他パツドを果りる必要がｌくなシ、チップの
面積も小さくできるという効果が得らｎる。As described above, in the case base according to the present invention, an integral bridge section is provided between the opposing circumferential walls across the center of the recess in which the integrated circuit chip is mounted, and a bridge section is also provided on this bridge section. Preparation and pregnancy. An electrode pad is also provided near the center of the integrated circuit chip housed in the package of the present invention,
By directly connecting the membrane wiring on the bridge portion and the chip center electrode pad with a metal wire, it is possible to eliminate the need to route the No. 1g line on the chip. As a result, it is possible to prevent characteristic deterioration due to the routing of signal lines on the chip, and there is no need to provide 111 and other pads only around the TEG, and the area of the chip can be reduced. nru.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）は本発明の一実施例に係るセラミックケー
ス基体に集積回路チップをマウントした状態の部分平面
図、同図（ｂ）は同図（ａ）のＡ−Ａ断面図、第２図は
従来のケース基体に集積回路チップをマウントした状態
の糾親図である。 １．１１・・・・・・セラミックケース基体、２・川・
・周壁、３，８・・・・・・膜配線、４．１４・・・・
・・集積回路チップ、５，６・・・・・・電極パッド、
７・・団・橋絡部、９・・・・・・金ｐｊ４線。FIG. 1(a) is a partial plan view of an integrated circuit chip mounted on a ceramic case base according to an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along line A-A in FIG. FIG. 2 is a diagram showing an integrated circuit chip mounted on a conventional case base. 1.11...Ceramic case base, 2. River.
・Peripheral wall, 3, 8...Membrane wiring, 4.14...
...Integrated circuit chip, 5,6... Electrode pad,
7...Group/Bridging Department, 9...Gold PJ4 line.

Claims (1)

【特許請求の範囲】[Claims] 集積回路チップをマウントするための中央凹所を有し、
この凹所を囲む厚い周壁上面に、前記集積回路チップの
電極パッドと金属線で接続される多数の膜配線が設けら
れた絶縁体のケース基体を備えた集積回路用パッケージ
において、さらに前記対向する周壁間をさし渡すように
橋絡部が一体に設けられ、かつ、この橋絡部上に、前記
金属線の一端が接続される膜配線が設けられていること
を特徴とする集積回路用パッケージ。has a central recess for mounting an integrated circuit chip;
In the integrated circuit package, the integrated circuit package is provided with an insulating case base having a thick peripheral wall surrounding the recess and a large number of membrane wirings connected to the electrode pads of the integrated circuit chip by metal wires on the top surface of the thick peripheral wall surrounding the recess. An integrated circuit for an integrated circuit, characterized in that a bridging portion is integrally provided across the peripheral walls, and a membrane wiring to which one end of the metal wire is connected is provided on the bridging portion. package.
JP60224242A 1985-10-07 1985-10-07 Package for integrated circuit Pending JPS6281741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60224242A JPS6281741A (en) 1985-10-07 1985-10-07 Package for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60224242A JPS6281741A (en) 1985-10-07 1985-10-07 Package for integrated circuit

Publications (1)

Publication Number Publication Date
JPS6281741A true JPS6281741A (en) 1987-04-15

Family

ID=16810715

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60224242A Pending JPS6281741A (en) 1985-10-07 1985-10-07 Package for integrated circuit

Country Status (1)

Country Link
JP (1) JPS6281741A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01163062A (en) * 1987-12-21 1989-06-27 Idemitsu N S G Kk Production of laminated sheet

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50674U (en) * 1973-05-01 1975-01-07
JPS5421168A (en) * 1977-07-18 1979-02-17 Kyushu Nippon Electric Semiconductor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50674U (en) * 1973-05-01 1975-01-07
JPS5421168A (en) * 1977-07-18 1979-02-17 Kyushu Nippon Electric Semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01163062A (en) * 1987-12-21 1989-06-27 Idemitsu N S G Kk Production of laminated sheet

Similar Documents

Publication Publication Date Title
KR100328906B1 (en) Method and device for joining leads inside lead-on chip of leadframe
JPH07147352A (en) Semiconductor integrated circuit device
JP2002093949A5 (en)
JPS6281741A (en) Package for integrated circuit
JPH0274046A (en) Semiconductor integrated circuit device
JP2681427B2 (en) Semiconductor device
US5719748A (en) Semiconductor package with a bridge for chip area connection
JPH061801B2 (en) Lead frame
US6479901B1 (en) Semiconductor device having interconnected external electrode pads and wire bonding pads
JPS59175145A (en) Lead frame
JP2539763B2 (en) Semiconductor device mounting method
JPS62202532A (en) Semiconductor device
JPH0364934A (en) Resin sealed semiconductor device
JPS62154769A (en) Semiconductor device
JPH0250623B2 (en)
JPH0545065B2 (en)
JP3078526B2 (en) Resin-sealed semiconductor device
JPH0547819A (en) Semiconductor device
JP2765124B2 (en) Lead frame
JPH0513658A (en) Lead frame for semiconductor device
JPS61125054A (en) Semiconductor device
JPS6081852A (en) Semiconductor device
JPS6228780Y2 (en)
JPS6286744A (en) Lsi chip
JPH01251645A (en) Package for semiconductor device