JPS6280764A - Floating point arithmetic unit for sum of product - Google Patents

Abstract

PURPOSE:To shorten a time required for the addition of floating point by normalizing only the finally accumulated result. CONSTITUTION:The exponential part data out of an output of an input register 71 to which accumulated output data are inputted from a double precision register 6 are applied to a subtractor 73 and the mantissa part data are applied to a maximum inverted code bit detecting circuit 72 and a shifter 74. The circuit 72 outputs a difference between the succeeding digit of a code bit and the digit of a maximum inverted code bit. The subtractor 73 subtracts the output of the circuit 72 from the exponential part data of the input register 71. The shifter 74 shifts the mantissa part data of the input register 71 left by regarding the output of the circuit 72 as a shifting variable. An output register outputs floating point data consisting of (e+2n-1) bits obtained by assigning an output consisting of (e) bits from the subtractor to the exponential part and an output consisting of (2n-1) bits from the shifter 74 on the basis of the outputs of the subtractor 73 and the shifter 74.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention can perform highly accurate product-sum calculations in a short time. Concerning floating point multiply-accumulate calculators.

[Conventional technology]

Product-sum operation, the product-sum operation performed by a device here involves multiplying two data strings input to the arithmetic device for each corresponding term of each data string, and sequentially adding the results of the multiplication. It is defined as an operation to find the internal debt.

In a conventional multiply-accumulator, when single-precision floating-point data is given as input data, a multiplication value is first obtained by normal floating-point multiplication, and then addition is performed.
In this case, the result of the floating point multiplication is obtained as single precision floating point data by rounding.

The above ordinary floating-point multiplication will be specifically described.

For example, as shown in FIG. 6(a), the numerical data 61 is
Exponent part is e bits, mantissa part is n bits (2's complement representation)
Suppose that it is given in floating point data format. When such data are multiplied, the exponent parts are added together and the mantissa parts are multiplied, and in particular, the mantissa part becomes 2n-1 bits by two's complement representation. This 2n-1 bit multiplication result is normalized, and by extracting its upper n bits, it is obtained as single-precision data.

As a result of the above, in the conventional product-sum calculation unit, the accuracy of the product-sum calculation decreases because addition is performed continuously using the multiplication value obtained as single-precision floating-point data.

Therefore, in order to perform the above product-sum operation with high precision, it is necessary to accumulate the 2n-1-bit mantissa multiplication result of the first multiplication without rounding it.To actually perform this, The exponent part of the e bit and 2n as shown in Figure 6 (5)
It is necessary to be able to perform the sum-of-products operation in the state of the double-precision floating point DEC 2 having a mantissa of -1 bit.

[Problem that the invention seeks to solve]

When performing floating point addition on double precision floating point data having an exponent part of e bits and a mantissa part of 2n-1 bits, it is necessary to shift the double precision mantissa part using a digit alignment shifter. Further, it is necessary to perform double-precision addition on the mantissa part, and finally perform double-precision shift on the addition result again using the normalization shifter.

To perform double-precision floating-point addition as described above, it is necessary to perform double-precision processing for each of the digit alignment shift, addition, and normalization shift. Therefore, compared to the case of performing single-precision floating-point addition, processing time is required, and the time required for the entire calculation becomes longer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a floating-point multiply-accumulate calculator that can omit part of the floating-point additions in multiply-accumulate operations including double-precision floating-point additions, thereby speeding up the computation time.

[Means for solving problems]

The floating-point multiply-accumulate calculator according to the present invention inputs two single-precision floating-point data strings, multiplies each corresponding term, and
A floating point multiplier that outputs multiplication data in double precision is inputted to a floating point multiplier that sequentially adds the multiplication results, and the multiplication data and sequential addition data are input, digit alignment and shift is performed on both data, and 2 a double-precision digit alignment shifter that outputs two double-precision mantissa parts and one exponent part;
A double-precision adder that adds two double-precision mantissa parts and outputs a double-precision addition output and an overflow output, and a 1-bit right shifter for the double-precision addition output when an overflow occurs in this double-precision adder. a bit right shift, an exponent part adder that adds 1 to the exponent part output from the double precision digit alignment shifter when an overflow occurs in the double precision adder, and the output of this exponent part adder as the exponent part. , a double-precision register that stores the sequential addition data with the output of the 1-bit right shifter as a mantissa and supplies the sequential addition data to the double-precision digit alignment shifter, and a final sequential addition in this double-precision register. The present invention is characterized in that it includes a left normalization shifter that performs left normalization of data.

[Effect]

In the present invention, the mantissa part of the multiplication result between two single-precision floating point data input to the floating point multiplier is
Do not round to single precision (input double precision to the double precision digit alignment shifter, align the digits with the output of the returned double precision register, then double the addition of the digit aligned double precision mantissa parts) When an overflow occurs in the mantissa addition described above, the mantissa is shifted to the right by 1 bit by a 1-bit right shifter, and 1 is added to the exponent part whose digits have been aligned by the exponent part adder.

If a loss of digits occurs during addition of the mantissa, the result of addition of the mantissa becomes a denormalized number. However, even if the number becomes a non-normalized number, normalization is not performed, and the sum-of-products operation is performed on the addition result without normalizing it one by one, thereby making it possible to omit the time required for double-precision normalization shift.

When performing a product-sum operation without normalization, the value of the exponent part may generally increase, but it will not decrease.

Therefore, when digit loss occurs and the value of the sum of products decreases, if you try to add a floating point multiplication result whose exponent part value is smaller than the value of the exponent part of the sum of products to the value of the sum of products, the digit shift will occur. , the lower bits of the mantissa of the floating-point multiplication result are
In the worst case, the number of bits lost is the same as the number of bits lost compared to normalization. In such a case, the arithmetic precision (number of digits in the calculation) of the mantissa is (number of digits in the mantissa) - (number of dropped digits).

However, since the mantissa addition is performed in double precision, even if a loss of digits occurs in the number of bits equivalent to single precision, the operational precision of the remaining number of bits equivalent to single precision is preserved.

Therefore, considering that the mantissa of the final operation result is obtained in single precision, a loss of digits equal to or less than the number of bits corresponding to single precision is allowed.

〔Example〕

The present invention will be described in detail below using the drawings.

FIG. 1 is a block diagram showing the overall configuration of a floating point multiply-accumulate calculator. As shown in the figure, the floating-point multiply-accumulate unit includes a floating-point multiplier 1, a double-precision digit alignment shift 2,
Double-precision adder 3, exponent adder 4, 1-bit right shifter 2, double-precision adder 3, exponent adder 4, 1-bit right shifter 5, double-precision register 6, and left normalization Arithmetic data 7
It consists of

In the above configuration, the floating point multiplier 1 has two input terminals 1a, and receives two e+n bits of floating point data through each input terminal 1a. In floating point data, the e bit is the exponent part and the n bit is the mantissa part. The floating point multiplier 1 outputs e+2n-1 bit multiplied data 8 based on two floating point data. In the multiplication data 8, the e bit is the exponent part, and the 2n-1 bits are the mantissa part. The multiplication data 8 and output data 9 of the double precision register 6, which will be described later, are input to the double precision digit alignment shifter 2. The double-precision digit alignment shifter 2 detects the larger value of the exponent part of the multiplication data 8 and the output data 9 and outputs it as an exponent part output 10, and also performs digit alignment for the mantissa part of the smaller exponent part value. After performing the shift, the mantissa part related to the multiplication data 8 and output data 9 is output as mantissa part 1.
Output as 1.12. The mantissa outputs 11 and 12 are input to the double precision adder 3. The double precision adder 3 receives two mantissa outputs 11°12 given from the double precision digit alignment shifter 2.
are added, and a double-precision addition output 13 is output. At the same time, the double-precision adder 3 outputs "1 n1 when no overflow occurs" when an overflow occurs during addition.
Outputs an overflow output 14 of 0''.

The exponent adder 4 receives the exponent output 10 from the double-precision digit alignment shifter 2 and the overflow output 1 from the double-precision adder 3.
4 is input, and the overflow output 14 is added to the least significant bit of the exponent output lO. In addition, the 1-bit right shifter 5 inputs the double-precision addition output 13 and the overflow output 14 from the double-precision adder 3, and the overflow output 14 is “
When the output is 1'', the double-precision addition output 13 is shifted to the right by 1 bit and output, and when the overflow output 14 is 0'', the output is output as is without performing the above-mentioned shift.

The output of the exponent part adder 4 and the output of the 1-bit right shifter 5 are applied to a double precision register 6. Double precision register 6
stores e+2n-1 bit floating point data with the output of the exponent part adder 4 as the exponent part and the output of the 1-bit right shifter 5 as the mantissa part. The floating point data thus stored in the double precision register 6 is provided to the digit alignment shifter 2 until the required accumulation is completed.

The left normalization operation 7 performs a left normalization operation on the e+2n-1 bit floating point data stored in the double precision register 6 after the required accumulation is completed. Here, the left normalization operation is to shift the entire mantissa part to the left so that a sign bit different from the leftmost sign bit in the mantissa part is placed in the next bit position, and then use the shift amount as an index. An operation that subtracts from a part. Specifically, using the example in Figure 6, if the mantissa part of the floating point data in Figure 6(C) is shifted to the left by m bits and m is subtracted from the exponent part, the result is shown in Figure 6(d). Floating point data like this is obtained after left normalization operation.

Next, the operation of the floating point multiply-accumulator with the above configuration is as follows.
This will be explained according to the flowcharts in FIGS. 2 and 3.

The flowcharts in Figures 2 and 3 are for connectors ■, ■, and O.
are combined by

First, when the multiply-accumulate operation is started, floating point multiplier 1's 2
Floating point data of e+n bits is input to each of the two input terminals 1a and la (step 31). The floating point multiplier 1 performs floating point multiplication on these input data (step S2), obtains multiplication data 8 of e+2n-1 bits, and outputs this.

Here, the exponent part of the multiplication data 8 is El, and the exponent part E1
The value of is expressed as 01, and the mantissa is expressed as Ml. On the other hand, the exponent part of the output data 9 given from the double precision register 6 is expressed as E2, the value of the exponent part E2 is expressed as e2, and the addend part M2.

In the next step, in double precision digit alignment shifter 2, E
Find the difference d=e1-e2 between l and E2 (step 33)
. When d is negative, the double-precision digit alignment shifter 2 shifts Ml by ld one digit in the direction between the left digits (step S4), sets the thus obtained Ml as the mantissa output 11 and the above M2 as the mantissa output 12, and outputs E2. is set as the exponent part output 10 (step 35). On the other hand, when d is positive, M2 is shifted 6 digits to the left (step S6), and the M2 thus obtained is
is set as the mantissa output 12, Ml is set as the mantissa output 11, and El is set as the exponent output 10 (step S7).

In the double-precision adder 3, the mantissa output 11 is determined as described above.
．． 12 is performed, and the double-precision adder 3 outputs a double-precision addition output 13 (step 38). It is determined whether an overflow has occurred in the addition in the double-precision adder 3 (step S9).

If an overflow occurs, the 1-bit right shifter 5
The mantissa part of the double-precision addition output 13 is shifted to the right by one bit (step 310), and the exponent part adder 4 adds 1 to the exponent part output 10 output from the double-precision digit alignment shifter 2 (step 511).

When performing the above 1-bit right shift on the mantissa,
The carry output of the double-precision addition output 13 is input to the most significant bit of the mantissa. If no overflow occurs, steps s1o and so are not executed.

The double-precision register 6 stores, as an intermediate result, floating point data whose exponent part is the output of the exponent part adder 4 and whose mantissa part is the output of the 1-bit right shifter 5 (step 512).
). Step 13 is a step of determining whether or not the accumulation has been completed. If the accumulation has not been completed, the process returns to step S1 and the steps 31 to S described above are performed on the next input data.
Repeat step 12.

When the accumulation is completed, the value stored in the double precision register 6 is normalized as the final result by the left normalization shifter 7 (step 514), the normalized output is output (step 515), and the process ends. do.

As is clear from the above operation, the floating point multiply-accumulator according to the present invention does not perform normalization point by point during the accumulation, but only normalizes the final result after the accumulation is completed. Therefore, the time required for floating point addition required for one accumulation can be reduced.

Next, detailed configurations of the double-precision digit alignment shifter 2 and left normalization shifter 7 will be explained.

FIG. 4 is a circuit diagram showing the structure of the double precision digit alignment shifter 2. As shown in the figure, the double precision digit alignment shifter 2 includes input registers 201, 202, subtracters 203, 204, input selectors 205, 206, and a shift amount selector 20.
7, a shifter 208, an exponent output selector 209, and a mantissa output selector 210 and 211.

In the above configuration, the multiplication data 8 is input to the first input register 201, and the output data 9 is input to the second register 202. The exponent part of the multiplication data 8 stored in the input register 201 and the exponent part of the output data 90 stored in the input register 202 are sent to the subtracters 203 and 20.
4, the subtracter 203 subtracts the exponent part of the input register 202 from the exponent part of the input register 201, and the subtracter 204 subtracts the exponent part of the input register 201 from the exponent part of the input register 202. This subtractor 203, 2
Each subtraction output of 04 is supplied to the shift amount selector 207.

Further, the subtracter 203 takes the most significant bit of the subtracted value as a code signal representing the magnitude relationship between the two exponent parts, and outputs it from O8. In this code signal,
The value of the exponent part of input register 201 is input to input register 202.
0 When the value of the exponent part is greater than or equal to the value of the exponent part, the value of C8 is "0", and conversely, when the value of the exponent part of the input register 201 is smaller than the value of the exponent part of the input register 202, the value of C8 is "1". becomes. This code signal is given to input selectors 205 , 206 , shift amount selector 207 and the like.

The mantissa parts of the input registers 201 and 202 are supplied to the input selectors 205 and 206, respectively.
Select one of the mantissa parts according to the value of 8.

That is, the input selector 205 selects the 2n-1 bit mantissa part of the input register 201 when the value of C8 is "0", and selects the 2n-1 bit mantissa part of the input register 201 when the value of C8 is "1".
Select the 2n-1 bit mantissa of 2. On the other hand, the input selector 206 selects the mantissa part of the input register 202 when the value of C3 is "0", and selects the mantissa part of the input register 201 when the value of O8 is "1". The output of the input selector 205 is the mantissa output selector 210.211.
and the output of the input selector 206 is input to the shifter 208.
given to.

The shift amount selector 207 selects the output of the subtracter 203 when the value of C8 is "0", and selects the output of the subtracter 204 when the value of C8O is "1". The output of shift amount selector 207 is given to shifter 208.

In the shifter 208, the output of the input selector 206 is shifted to the right by the number of bits specified by the output of the shift amount selector 207. The output of shifter 208 is given to mantissa output selectors 210 and 211.

The exponent output selector 209 is supplied with the exponent outputs of the input registers 201 and 202 and the code signal of the subtracter 203. Exponent output selector 209 selects the exponent output of input register 201 when the value of O8 is "0", and selects the exponent output of input register 202 when the value of C8O is "1". The exponent part output selector 209 outputs the exponent part output 10.

A sign signal is supplied from the subtracter 203 to the mantissa output selectors 210 and 211, and the sign signal causes the mantissa output selectors 210 and 211 to perform the following selector operation. That is, in the mantissa output selector 210,
When the value of C8 is "0", the output of the input selector 205 is selected, and when the value of O8 is "1", the output of the shifter 208 is selected and output as the mantissa output 11. Furthermore, the mantissa output selector 211 selects the output of the shifter 208 when the value of C8 is "0", and selects the output of the shifter 208 when the value of C8 is "1".
”, the output of the input selector 205 is selected and output as the mantissa output 12.

As described above, in the double-precision digit alignment shifter 2, among the multiplication data 8 and the output data 9 input to the input registers 201 and 202, the exponent part with the larger value is the exponent part output 1.
0, and the mantissa part of 7'-1, which has a small exponent part, is shifted to the right by the difference in the exponent parts, thereby producing a mantissa output of 11.12.

FIG. 5 is a circuit diagram showing the configuration of the left normalization shifter 7.

The left normalization shifter 7 has an input register 7 as shown in the figure.
1, a maximum sign bit detection circuit 72, a subtracter 73, a shifter 74, and an output register 75.

In the above configuration, the output data accumulated from the double precision register 6 is input to the input register 71. At the output of the input register 71, the exponent data is sent to the subtracter 7.
3, and the mantissa data is also provided to the maximum sign bit detection circuit 72 and shifter 74. The largest plus sign bit detection circuit 72 detects the position of the largest plus sign bit (the largest bit having a bit different from the sign bit among the lower bits of the sign bit) of the mantissa data,
Outputs the digit difference between the next digit bit of the sign bit and the largest sign bit. The output of the maximum sign bit detection circuit 72 is given to a subtracter 73 and a shifter 74.

In the subtracter 73, the output of the maximum plus sign bit detection circuit 72 is subtracted from the exponent part data of the input register 71. Further, in the shifter 74, the mantissa' part data of the input register 71 is shifted to the left using the output of the maximum sign bit detection circuit 72 as the shift amount. Based on the outputs of the subtracter 73 and shifter 74, the output register 75
The output of the e bit of the subtracter 73 is used as the exponent part, and the shifter 74
e+2n-1 with the 2n-1 bits of output as the mantissa part
Output bit floating point data.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in a floating-point multiply-accumulate unit that performs double-precision point accumulation on floating-point multiplication results obtained sequentially, each addition in the floating-point accumulation is normalized. By performing normalization only on the final accumulation result without performing a conversion shift, the time required for floating-point addition can be shortened, and the time required for the entire floating-point multiply-accumulate operation can be shortened. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a floating-point multiply-accumulate unit according to the present invention, FIG. 2 is a flowchart for explaining the operation, FIG. 3 is a flowchart for explaining the operation, and FIG. Figure 5 is a circuit diagram showing the detailed configuration of the precision digit alignment shifter, Figure 5 is a circuit diagram showing the detailed configuration of the left normalization shifter, Figure 6 is a diagram showing normal floating point data representation and double precision floating point data representation. It is. 1... Floating point multiplier 2... Double precision digit alignment shifter 3...
・Double precision adder 4...Exponent adder 5...1 bit right shifter 6...Double precision register 7...Left normalization shifter agent Patent Attorney Yoshiyuki Iwasa Figure 1 Figure 2 Figure 6

Claims (1)

[Claims] (1) A floating-point multiplier that inputs two single-precision floating-point data strings, multiplies each corresponding term, and sequentially adds the multiplication results. A floating-point multiplier that outputs the multiplied data in double precision. Then, input the multiplication data and sequential addition data, perform digit alignment shift on both data,
a double-precision digit shifter that outputs two double-precision mantissa parts and one exponent part; a double-precision adder that adds the two double-precision mantissa parts and outputs a double-precision addition output and an overflow output; a 1-bit right shifter that shifts the double-precision addition output by 1 bit to the right when an overflow occurs in the precision adder; and an exponent output from the double-precision digit alignment shifter when an overflow occurs in the double-precision adder. an exponent adder that adds 1 to the exponent adder; the output of the exponent adder is the exponent; the output of the 1-bit right shifter is the mantissa; the sequentially added data is stored; A floating-point product-sum calculator comprising: a double-precision register that supplies this sequential addition data to a shifter; and a left normalization shifter that left-normalizes the final sequential addition data in the double-precision register.