JPS627775B2 - - Google Patents

Info

Publication number
JPS627775B2
JPS627775B2 JP1994381A JP1994381A JPS627775B2 JP S627775 B2 JPS627775 B2 JP S627775B2 JP 1994381 A JP1994381 A JP 1994381A JP 1994381 A JP1994381 A JP 1994381A JP S627775 B2 JPS627775 B2 JP S627775B2
Authority
JP
Japan
Prior art keywords
output
voltage
transistor
circuit
switch element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1994381A
Other languages
Japanese (ja)
Other versions
JPS57135679A (en
Inventor
Yoshihiko Fukuhara
Takashi Iwase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1994381A priority Critical patent/JPS57135679A/en
Publication of JPS57135679A publication Critical patent/JPS57135679A/en
Publication of JPS627775B2 publication Critical patent/JPS627775B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33561Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having more than one ouput with independent control

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Description

【発明の詳細な説明】 本発明は、疑似負荷を有するDC―DCコンバー
タ、特に2つの出力を有するDC―DCコンバータ
において、各出力に接続された負荷の値に関係な
く安定な出力を得ると共に電力損を減小した疑似
負荷を有するDC―DCコンバータに関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a DC-DC converter with a pseudo load, particularly a DC-DC converter with two outputs, which can obtain stable output regardless of the value of the load connected to each output. This invention relates to a DC-DC converter with a pseudo load that reduces power loss.

DC―DCコンバータを構成する変成器に2つの
出力巻線を設け、各出力巻線に発生するパルス電
圧を整流・平滑して2つの直流出力を得て、かつ
1つの直流出力電圧を安定化するため該DC―DC
コンバータを構成するスイツチ素子の開閉比を制
御し、他の直流出力電圧を安定化するために直列
制御安定化回路を設けることにより、2つの安定
な直流電圧を得る構成は従来から用いられてき
た。第1図はこの種の回路に疑似負荷を設けた構
成の一例であり、1は直流電源、2は変成器、3
はスイツチ素子、4,5,15,16は整流器、
6,17は塞流線輪、7,18はコンデサ、8,
9は第1の出力端子、10,24は出力負荷、1
1は制御回路、12,20は基準電圧源、13,
21は誤差増幅器、14は開閉制御回路、19は
電圧降下素子、22,23は第2の出力端子、2
5は抵抗である。
Two output windings are provided in the transformer that constitutes the DC-DC converter, and the pulse voltage generated in each output winding is rectified and smoothed to obtain two DC outputs, and one DC output voltage is stabilized. To do so, the DC-DC
Conventionally, a configuration has been used to obtain two stable DC voltages by controlling the switching ratio of the switch elements that make up the converter and providing a series control stabilization circuit to stabilize the other DC output voltages. . Figure 1 is an example of a configuration in which a pseudo load is provided in this type of circuit, where 1 is a DC power supply, 2 is a transformer, and 3 is a transformer.
is a switch element, 4, 5, 15, 16 are rectifiers,
6, 17 are blockage rings, 7, 18 are condesa, 8,
9 is the first output terminal, 10 and 24 are the output loads, 1
1 is a control circuit, 12, 20 is a reference voltage source, 13,
21 is an error amplifier, 14 is a switching control circuit, 19 is a voltage drop element, 22 and 23 are second output terminals, 2
5 is resistance.

直流電源1と変成器2の第1の巻線n1とトラン
ジスタを用いたスイツチ素子3とが直列に接続さ
れ、スイツチ素子3の開閉により生ずるパルス電
圧が変成器2の第1の巻線n1に印加され、変成器
2の第2の巻線n2に誘起したパルス電圧を整流器
4,5で整流し、塞流線輪6とコンデンサ7とで
構成される平滑回路で平滑し、第1の出力端子
8,9間に第1の直流出力を得て出力負荷10に
供給し、第1の出力端子8,9間の直流電圧と制
御回路11における基準電圧源12の電圧との差
を誤差増幅器13で増幅し、誤差増幅器13の出
力に応じて出力開閉比を可変する開閉制御回路1
4の出力をスイツチ素子3の制御端子すなわちベ
ース電極に印加することにより、第1の出力端子
8,9間の電圧を基準電圧源12の電圧と一致す
るようにスイツチ素子3の開閉比を制御するよう
構成されている。そして更に第2の出力を得るた
め変成器2の第3の巻線n3に誘起したパルス電圧
を整流器15,16で整流し、塞流線輪17とコ
ンデンサ18とで構成される平滑回路で平滑し、
コンデンサ18の端子間に他の直流電圧を得て、
上記他の直流電圧を安定化するため第2の出力端
子22との間にトランジスタを用いた電圧降下素
子19を接続し、第2の出力端子22,23間の
電圧と基準電圧源20の電圧との差を誤差増幅器
21で増幅して電圧降下素子19の制御端子すな
わちベース電極に印加することにより第2の出力
端子22,23間の電圧を基準電圧源20の電圧
と等しくなるように電圧降下素子19の端子間す
なわちコレクタ・エミツタ電極間電圧を制御し、
出力負荷24に安定な直流電圧が供給されるよう
構成される。
The DC power supply 1, the first winding n1 of the transformer 2, and the switch element 3 using a transistor are connected in series, and the pulse voltage generated by opening and closing the switch element 3 is applied to the first winding n1 of the transformer 2. 1 , the pulse voltage induced in the second winding n2 of the transformer 2 is rectified by rectifiers 4 and 5, smoothed by a smoothing circuit composed of a blocking wire 6 and a capacitor 7, and then A first DC output is obtained between the first output terminals 8 and 9 and supplied to the output load 10, and the difference between the DC voltage between the first output terminals 8 and 9 and the voltage of the reference voltage source 12 in the control circuit 11 is A switching control circuit 1 that amplifies the output switching ratio using an error amplifier 13 and varies the output switching ratio according to the output of the error amplifier 13.
By applying the output of 4 to the control terminal, that is, the base electrode of the switch element 3, the switching ratio of the switch element 3 is controlled so that the voltage between the first output terminals 8 and 9 matches the voltage of the reference voltage source 12. is configured to do so. Furthermore, in order to obtain a second output, the pulse voltage induced in the third winding n3 of the transformer 2 is rectified by rectifiers 15 and 16, and a smoothing circuit consisting of a blocking wire 17 and a capacitor 18 is used. smooth,
Obtaining another DC voltage across the terminals of the capacitor 18,
In order to stabilize the other DC voltage mentioned above, a voltage drop element 19 using a transistor is connected between the second output terminal 22 and the voltage between the second output terminals 22 and 23 and the voltage of the reference voltage source 20. The difference between the two output terminals 22 and 23 is amplified by the error amplifier 21 and applied to the control terminal, that is, the base electrode of the voltage drop element 19, so that the voltage between the second output terminals 22 and 23 is made equal to the voltage of the reference voltage source 20. Controlling the voltage between the terminals of the drop element 19, that is, between the collector and emitter electrodes,
The output load 24 is configured to be supplied with a stable DC voltage.

第1図に示す回路は第1の出力端子9と第2の
出力端子22を接続してこれを地気として、第1
の出力端子8には正極性の安定な直流電圧が供給
され、第2の出力端子23には負極性の安定な直
流電圧が供給される。
The circuit shown in FIG. 1 connects the first output terminal 9 and the second output terminal 22 and uses this as the
A stable DC voltage of positive polarity is supplied to the output terminal 8 of , and a stable DC voltage of negative polarity is supplied to the second output terminal 23 .

第2図は第1図の動作を示す特性であり、横軸
は出力負荷に流れる出力電流I1を示し、縦軸はス
イツチ素子3の開閉比Dと第1の出力端子8,9
間の電圧V1とコンデンサ18の端子間電圧V2′と
第2の出力端子22,23間の電圧V2とを示し
ている。出力電流I1が大きい状態では、スイツチ
素子3が導通している期間に整流器4を通して塞
流線輪6に励磁電流が蓄積し、スイツチ素子3の
遮断により塞流線輪6に蓄積された励磁電流は整
流器5に転流して流れ続け再びスイツチ素子3が
導通することとなり、上記励磁電流が整流器5を
通してコンデンサ7と出力負荷10に完全に放出
されることはない。このため、出力電流I1を次第
に減小しても主スイツチの開閉比Dは近似的に変
成器2の第2の巻線n2に誘起するパルス電圧波高
値と第1の出力端子8,9間の電圧の比となりほ
ぼ一定値を保つ。出力電流I1が零に近ずくと第1
の出力電圧V1を一定に保つように制御回路11
はスイツチ素子3の開閉比Dを零に近ずけるよう
に制御する。この開閉比Dが変化する状態と前記
の開閉比Dがほぼ一定値である状態の境界(第2
図における出力電流I1がIc)はスイツチ素子3
が遮断から導通に変る時刻に前記塞流線輪6の励
磁電流の放出が完了した場合となる。第1の出力
電流I1がIc以上の場合にはコンデンサ18の端
子間電圧V2′は電圧降下素子19が十分に動作し
得る程大きい値となるが、第1の出力電流I1がI
c以下になると前記の通りスイツチ素子3の開閉
比Dが小さくなるため出力負荷24に所望の電流
を供給するとコンデンサ18の端子間電圧V2′は
低下してしまう。この時電圧降下素子19の入力
端(コレクタ電極)の電位が基準電圧源20の電
位より下つてしまうため第2の出力端子22,2
3間の電圧V2を所定の一定値に保つことはでき
ず電圧V2は低下する。出力負荷10および24
のあらゆる状態に拘らず第1の出力端子8,9間
の電圧V1と第2の出力端子22,23間の電圧
V2とを一定に保つために、通常見かけ上第1の
出力端子8,9から出力電流Ic以上の電流を流
すのと等価な疑似負荷となる抵抗25がコンデン
サ7と並列接続される。しかし、抵抗Rは常に電
流Ic以上の電流を消費するため、電力損失の増
加と共にスイツチ素子3および整流器4,5に対
し大きな電流が流せるものが要求される。
FIG. 2 shows characteristics showing the operation in FIG. 1, where the horizontal axis shows the output current I1 flowing to the output load, and the vertical axis shows the switching ratio D of the switch element 3 and the first output terminals 8, 9.
1 , the voltage V 2 ' between the terminals of the capacitor 18, and the voltage V 2 between the second output terminals 22 and 23. When the output current I1 is large, excitation current accumulates in the blocking wire 6 through the rectifier 4 while the switch element 3 is conducting, and the excitation current accumulated in the blocking wire 6 due to the cutoff of the switch element 3 The current is commutated to the rectifier 5 and continues to flow, and the switch element 3 becomes conductive again, so that the excitation current is not completely discharged through the rectifier 5 to the capacitor 7 and the output load 10. Therefore, even if the output current I 1 is gradually reduced, the switching ratio D of the main switch is approximately equal to the peak value of the pulse voltage induced in the second winding n 2 of the transformer 2 and the peak value of the pulse voltage induced in the second winding n 2 of the transformer 2. The voltage ratio between 9 and 9 remains almost constant. When the output current I 1 approaches zero, the first
The control circuit 11 maintains the output voltage V 1 constant.
controls the switching ratio D of the switch element 3 so as to approach zero. The boundary between the state where the switching ratio D changes and the state where the switching ratio D is approximately constant (the second
In the figure, the output current I 1 ( I c ) is the switch element 3
This is the case when the discharge of the excitation current from the blocking coil 6 is completed at the time when the current changes from cutoff to conduction. When the first output current I 1 is greater than or equal to I c , the voltage V 2 ' between the terminals of the capacitor 18 is large enough to allow the voltage drop element 19 to operate sufficiently; I
If the value is less than c , the switching ratio D of the switch element 3 becomes small as described above, so that when a desired current is supplied to the output load 24, the voltage V 2 ' between the terminals of the capacitor 18 decreases. At this time, since the potential at the input end (collector electrode) of the voltage drop element 19 falls below the potential of the reference voltage source 20, the second output terminals 22, 2
The voltage V 2 between the two terminals cannot be maintained at a predetermined constant value, and the voltage V 2 decreases. Output loads 10 and 24
The voltage V 1 between the first output terminals 8 and 9 and the voltage between the second output terminals 22 and 23
In order to keep V 2 constant, a resistor 25 is connected in parallel with the capacitor 7, which normally serves as a pseudo load equivalent to flowing a current that is apparently higher than the output current I c from the first output terminals 8 and 9. However, since the resistor R always consumes a current greater than the current I c , the switch element 3 and the rectifiers 4 and 5 are required to be capable of passing a large current as power loss increases.

本発明は、これらの欠点を解決するため、出力
負荷10に供給する電流が減小した場合のみ疑似
負荷に電流を流すことにより電力損失を減小させ
たものであり、以下図面について詳細に説明す
る。
In order to solve these drawbacks, the present invention reduces power loss by passing current through the pseudo load only when the current supplied to the output load 10 decreases, and will be described in detail with reference to the drawings below. do.

第3図は本発明による疑似負荷を有するDC―
DCコンバータの一実施例であり、30は疑似負
荷回路、31は抵抗、32はトランジスタ、33
は基準電圧源、34は電圧比較器であり、第1の
出力端子8,9間に抵抗31とトランジスタ32
とが直列に接続され、電圧比較器34は第1の出
力端子9または第2の出力端子22の電位に対し
て基準電圧源33の電圧と第2の出力を安定化す
るための電圧降下素子19の入力端(コレクタ電
極)の電圧とを比較して、基準電圧源33の電圧
に対して電圧降下素子19の入力端の電圧が小さ
ければ電圧比較器34の出力が高電位となりトラ
ンジスタ32を導通させるように接続されてい
る。ここで基準電圧源33の電圧を電圧降下素子
19が正常に動作し得る入出力間電圧すなわちコ
レクタ・エミツタ間電圧以上に選定しておけば、
出力負荷10に流れる電流が減小して制御回路1
1を通してスイツチ素子3の開閉比Dが減小して
コンデンサ18の端子間電圧が低下した場合に、
電圧降下素子19の入出力間電圧が基準電圧源3
3の電圧以下に低下すると、電圧比較器34を通
してトランジスタ32を導通させ疑似負荷電流を
流し、制御回路11を通してスイツチ素子3の開
閉比Dが一定値以下に低下しない動作をおこなう
から、電圧降下素子19は出力負荷10のあらゆ
る状態に対して正常に動作し、出力端子22,2
3間に安定化電圧が得られる。
FIG. 3 shows a DC--
This is an example of a DC converter, where 30 is a pseudo load circuit, 31 is a resistor, 32 is a transistor, and 33
is a reference voltage source, 34 is a voltage comparator, and a resistor 31 and a transistor 32 are connected between the first output terminals 8 and 9.
are connected in series, and the voltage comparator 34 is a voltage drop element for stabilizing the voltage of the reference voltage source 33 and the second output with respect to the potential of the first output terminal 9 or the second output terminal 22. 19, and if the voltage at the input end of the voltage drop element 19 is smaller than the voltage of the reference voltage source 33, the output of the voltage comparator 34 becomes a high potential and the transistor 32 is Connected for conduction. If the voltage of the reference voltage source 33 is selected to be higher than the input-output voltage at which the voltage drop element 19 can operate normally, that is, the collector-emitter voltage, then
The current flowing through the output load 10 decreases and the control circuit 1
1, when the switching ratio D of the switch element 3 decreases and the voltage between the terminals of the capacitor 18 decreases,
The voltage between the input and output of the voltage drop element 19 is the reference voltage source 3
When the voltage drops below 3, the transistor 32 is made conductive through the voltage comparator 34 to flow a pseudo load current, and the switching ratio D of the switch element 3 is operated through the control circuit 11 so that it does not fall below a certain value. 19 operates normally under all conditions of the output load 10, and the output terminals 22, 2
A stabilized voltage is obtained between 3 and 3.

第4図は疑似負荷回路30の他の一構成例であ
り、40はトランジスタ、41,42は抵抗であ
る。端子Aは第1の出力端子8に、端子Bは第1
の出力端子9に、端子Cは電圧降下素子19の入
力端に各々接続され、トランジスタ40のベース
電極は抵抗41を通して端子Cに、トランジスタ
40のエミツタ電極は端子Bに、トランジスタ4
0のコレクタ電極はトランジスタ32のベース電
極に接続されると共に抵抗42を通して端子Aに
接続されている。端子Bの電位に対して端子Cの
電位がトランジスタ40を導通させるために必要
なベース・エミツタ間電圧よりも高ければトラン
ジスタ40が導通し、トランジスタ32は遮断す
るから疑似負荷電流が流れず、電圧降下素子19
の入出力間電圧が該ベース・エミツタ間電圧より
低下するとトランジスタ40が遮断し、トランジ
スタ32が導通し抵抗31を通して疑似負荷電流
を流す。この場合第3図に示す基準電圧源33の
電圧は上記ベース・エミツタ間電圧に該当する。
また抵抗31は疑似負荷電流を制限する目的で挿
入されるが、当然第2図に示した出力電流Ic
上の電流を流せる値が必要である。
FIG. 4 shows another configuration example of the pseudo load circuit 30, in which 40 is a transistor, and 41 and 42 are resistors. Terminal A is connected to the first output terminal 8, and terminal B is connected to the first output terminal 8.
The terminal C is connected to the output terminal 9 of the voltage drop element 19, the base electrode of the transistor 40 is connected to the terminal C through the resistor 41, the emitter electrode of the transistor 40 is connected to the terminal B, and the terminal C is connected to the input terminal of the voltage drop element 19.
The collector electrode of the transistor 32 is connected to the base electrode of the transistor 32, and is also connected to the terminal A through the resistor 42. If the potential at terminal C with respect to the potential at terminal B is higher than the base-emitter voltage required to make transistor 40 conductive, transistor 40 becomes conductive and transistor 32 is cut off, so no pseudo load current flows and the voltage decreases. Falling element 19
When the input/output voltage of the transistor 40 becomes lower than the base-emitter voltage, the transistor 40 is cut off, and the transistor 32 becomes conductive, causing a pseudo load current to flow through the resistor 31. In this case, the voltage of the reference voltage source 33 shown in FIG. 3 corresponds to the base-emitter voltage.
Further, the resistor 31 is inserted for the purpose of limiting the pseudo load current, but naturally it must have a value that allows a current greater than the output current I c shown in FIG. 2 to flow.

第5図は疑似負荷回路30の更に他の構成例で
あり、50は抵抗、51はコンデンサであり、ト
ランジスタ40のコレクタ電極とトランジスタ3
2のベース電極との間に抵抗50が接続され、ト
ランジスタ32のベース電極とコレクタ電極との
間にコンデンサ51が接続されている。
FIG. 5 shows still another configuration example of the pseudo load circuit 30, in which 50 is a resistor, 51 is a capacitor, and the collector electrode of the transistor 40 and the transistor 3
A resistor 50 is connected between the base electrode of the transistor 32 and the collector electrode of the transistor 32, and a capacitor 51 is connected between the base electrode and the collector electrode of the transistor 32.

前述した疑似負荷回路の動作のように出力負荷
10に流れる電流が小さいと抵抗31とトランジ
スタ32を通して疑似負荷電流が流れコンデンサ
18の端子間電圧を一定値以上に保持する動作
は、制御回路11を通して第1の出力端子8,9
間の電圧を一定に保つ負帰還制御系の他に、変成
器2の第3の巻線から整流器15,16、塞流線
輪17、コンデンサ18で構成される整流・平滑
回路、さらに疑似負荷回路を通り制御回路11に
よりスイツチ素子3の開閉比Dを制御する第2の
負帰還制御系を構成している。上記2重の負帰還
制御系で構成される電源回路を安定に動作させる
ためには必要に応じて疑似負荷回路の応答特性を
落す必要が生ずる。第5図はトランジスタ32に
おいて抵抗50とコンデンサ51により公知のミ
ラー積分動作をさせるものであり、その他の動作
は第4図と全く同一で、抵抗50とコンデンサ5
1の値を適正に選定することにより極めて安定な
動作が得られる。
As in the operation of the pseudo load circuit described above, when the current flowing through the output load 10 is small, a pseudo load current flows through the resistor 31 and the transistor 32, and the operation of maintaining the voltage across the terminals of the capacitor 18 above a certain value is carried out through the control circuit 11. First output terminal 8, 9
In addition to the negative feedback control system that keeps the voltage between A second negative feedback control system is configured in which the switching ratio D of the switch element 3 is controlled by the control circuit 11 through the circuit. In order to stably operate the power supply circuit constituted by the double negative feedback control system, it is necessary to reduce the response characteristics of the pseudo load circuit as necessary. In FIG. 5, a well-known Miller integral operation is performed using a resistor 50 and a capacitor 51 in a transistor 32, and the other operations are exactly the same as in FIG.
By appropriately selecting the value 1, extremely stable operation can be obtained.

以上説明したように、本発明によれば、第1の
出力電圧を安定化したDC―DCコンバータを構成
する変成器2に第3の巻線を設けて、該第3の巻
線に誘起するパルス電圧を整流・平滑して直列制
御安定化回路を通して第2の安定化した出力電圧
を得る電源回路において、第1の出力端子間に抵
抗31とトランジスタ32の直列回路を接続し、
該直列制御安定化回路を構成する電圧降下素子1
9が正常動作をおこなうために必要な電圧降下素
子19の入出力間電圧以上の電圧を有する基準電
圧源33を設け、基準電圧源33の電圧と電圧降
下素子19の入力端の電圧とを電圧比較器34で
比較してトランジスタ32を制御することによ
り、第1の出力端子8,9に接続された出力負荷
10のあらゆる状態に対して第2の出力端子2
2,23間に安定な第2の出力電圧を得ることが
でき、さらに抵抗31とトランジスタ32とに流
れる疑似負荷電流は電圧降下素子19の入力端電
圧が所定の値以下に低下しようとする場合のみ、
すなわち出力負荷10に流れる電流がIc以下に
低下した場合のみ流れるため従来の疑似負荷を有
するDC―DCコンバータに比べて電力損失を低下
される。更に本発明による疑似負荷を有するDC
―DCコンバータにおいては電圧降下素子19の
入力端電圧に応じて疑似負荷電流が流れるため、
例えば塞流線輪のインダクタンスが何らかの原因
で変化して第2図に示すIcの値が変化してもコ
ンデンサ18の電圧は上記入力端電圧の低下開始
点に自動的に追従する利点がある。一方、第1図
に示した従来の構成においては例えば上記塞流線
輪のインダクタンスの製造偏差または使用中の偏
差等を考慮して余分の疑似負荷電流を流せる抵抗
値が抵抗25に対して要求されるため、より多く
の電力損失が生ずる。また本発明の場合、より多
くの電力損失が減小すると共にスイツチ素子3、
整流器4,5の電流容量も小さくてよい利点があ
る。
As explained above, according to the present invention, the transformer 2 constituting the DC-DC converter in which the first output voltage is stabilized is provided with the third winding, and the voltage induced in the third winding is In a power supply circuit that rectifies and smoothes a pulse voltage and obtains a second stabilized output voltage through a series control stabilization circuit, a series circuit of a resistor 31 and a transistor 32 is connected between the first output terminals,
Voltage drop element 1 constituting the series control stabilization circuit
A reference voltage source 33 having a voltage higher than the voltage between the input and output of the voltage drop element 19 necessary for normal operation of the voltage drop element 19 is provided, and the voltage of the reference voltage source 33 and the voltage at the input end of the voltage drop element 19 are set to a voltage. By comparing with the comparator 34 and controlling the transistor 32, the second output terminal 2 is
A stable second output voltage can be obtained between 2 and 23, and the pseudo load current flowing through the resistor 31 and the transistor 32 is reduced when the input terminal voltage of the voltage drop element 19 is about to drop below a predetermined value. only,
That is, since the current flows only when the current flowing through the output load 10 falls below I c , power loss is reduced compared to a conventional DC-DC converter having a pseudo load. Furthermore, the DC with pseudo load according to the present invention
- In the DC converter, a pseudo load current flows according to the input terminal voltage of the voltage drop element 19, so
For example, even if the inductance of the blockage wire changes for some reason and the value of I c shown in FIG. . On the other hand, in the conventional configuration shown in FIG. 1, the resistor 25 is required to have a resistance value that allows an extra pseudo load current to flow, taking into account manufacturing deviations or deviations during use of the inductance of the above-mentioned blockage wire, for example. This results in more power loss. Further, in the case of the present invention, more power loss is reduced and the switch element 3,
There is an advantage that the current capacity of the rectifiers 4 and 5 is also small.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の疑似負荷を有するDC―DCコン
バータの回路例、第2図は第1図の動作を説明す
るための特性図、第3図は本発明による疑似負荷
を有するDC―DCコンバータの一実施例、第4図
は第3図における疑似負荷回路の一構成例、第5
図は第3図における疑似負荷回路の他の構成例で
ある。 1……直流電源、2……変成器、3……スイツ
チ素子、4,5,15,16……整流器、6,1
7……塞流線輪、7,18,51……コンデン
サ、8,9……第1の出力端子、10,24……
出力負荷、11……制御回路、12,20,33
……基準電圧源、13,21……誤差増幅器、1
4……開閉制御回路、19……電圧降下素子、2
2,23……第2の出力端子、25,31,4
1,42,50……抵抗、30……疑似負荷回
路、32,40……トランジスタ、34……電圧
比較器。
Fig. 1 is a circuit example of a conventional DC-DC converter with a pseudo load, Fig. 2 is a characteristic diagram for explaining the operation of Fig. 1, and Fig. 3 is a DC-DC converter with a pseudo load according to the present invention. One embodiment, FIG. 4 is an example of the configuration of the pseudo load circuit in FIG. 3, and FIG.
The figure shows another example of the configuration of the pseudo load circuit in FIG. 3. 1... DC power supply, 2... Transformer, 3... Switch element, 4, 5, 15, 16... Rectifier, 6, 1
7... Blocking wire, 7, 18, 51... Capacitor, 8, 9... First output terminal, 10, 24...
Output load, 11...Control circuit, 12, 20, 33
... Reference voltage source, 13, 21 ... Error amplifier, 1
4... Opening/closing control circuit, 19... Voltage drop element, 2
2, 23...second output terminal, 25, 31, 4
1, 42, 50...Resistor, 30...Pseudo load circuit, 32, 40...Transistor, 34...Voltage comparator.

Claims (1)

【特許請求の範囲】[Claims] 1 直流電源と変成器の第1の巻線とスイツチ素
子とを直列に接続し、該スイツチ素子の開閉によ
り上記変成器の第2の巻線に発生したパルス電圧
を整流・平滑して得られる第1の出力の電圧を所
望の基準電圧と比較して上記スイツチ素子の開閉
比を制御することにより該第1の出力を安定化
し、上記変成器の第3の巻線に発生したパルス電
圧を整流・平滑して得られた直流電圧を直列制御
安定化回路の入力として該直列制御安定化回路の
出力に安定化された第2の出力を得て、上記第1
の出力と上記第2の出力との各片側端子を接続し
て共通の地気とすることにより安定化された正極
と負極の2出力を得る直流安定化電源において、
上記第1の出力に抵抗とトランジスタとの直列回
路を接続し、上記直列制御安定化回路が正常に動
作し得る最低の電圧降下値以上の第2の基準電圧
と上記直列制御安定化回路の入力端の電圧とを比
較して上記トランジスタを制御することを特徴と
する疑似負荷を有するDC―DCコンバータ。
1 A DC power source, the first winding of the transformer, and a switch element are connected in series, and the pulse voltage generated in the second winding of the transformer is rectified and smoothed by opening and closing of the switch element. The first output is stabilized by comparing the voltage of the first output with a desired reference voltage and controlling the switching ratio of the switch element, and the pulse voltage generated in the third winding of the transformer is stabilized. The DC voltage obtained by rectifying and smoothing is input to a series control stabilizing circuit to obtain a second output stabilized as the output of the series control stabilizing circuit.
In a DC stabilized power supply that obtains two stabilized outputs, a positive pole and a negative pole, by connecting the terminals on each side of the output and the second output to form a common ground,
A series circuit of a resistor and a transistor is connected to the first output, and a second reference voltage higher than the lowest voltage drop value at which the series control stabilization circuit can operate normally is input to the series control stabilization circuit. A DC-DC converter having a pseudo load, characterized in that the transistor is controlled by comparing the voltage at the terminal.
JP1994381A 1981-02-12 1981-02-12 Dc/dc converter with quasi-load Granted JPS57135679A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1994381A JPS57135679A (en) 1981-02-12 1981-02-12 Dc/dc converter with quasi-load

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1994381A JPS57135679A (en) 1981-02-12 1981-02-12 Dc/dc converter with quasi-load

Publications (2)

Publication Number Publication Date
JPS57135679A JPS57135679A (en) 1982-08-21
JPS627775B2 true JPS627775B2 (en) 1987-02-19

Family

ID=12013283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1994381A Granted JPS57135679A (en) 1981-02-12 1981-02-12 Dc/dc converter with quasi-load

Country Status (1)

Country Link
JP (1) JPS57135679A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59153462A (en) * 1983-02-17 1984-09-01 Tdk Corp Dc/dc converter
JPH0832126B2 (en) * 1986-01-27 1996-03-27 三菱電機株式会社 Power supplies for circuits and disconnectors
DE3633518A1 (en) * 1986-10-02 1988-04-14 Philips Patentverwaltung CLOCKED DC CONVERTER
JP5035851B2 (en) * 2008-05-20 2012-09-26 Ykk Ap株式会社 Joinery
DE102013203014B4 (en) * 2013-02-25 2022-10-06 Vitesco Technologies GmbH Voltage supply device with a circuit arrangement for rapidly discharging at least one capacitor

Also Published As

Publication number Publication date
JPS57135679A (en) 1982-08-21

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