JPS627709B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a field effect transistor having an insulated control electrode (gate).

The present invention is directed to obtaining a low voltage, high speed operation, high integration density semiconductor integrated circuit device which is composed of composite field transistors.

Conventionally, in order to obtain the same effect as the present invention, complementary transistors (Complementary MOS
Trs) were commonly used. A complementary transistor is a circuit in which a P-channel MOS transistor and an N-channel MOS transistor are separated on the same semiconductor substrate plane, their respective functions are ensured, and appropriate wiring is formed.

Conventional complementary transistors are already commonly manufactured as semiconductor integrated circuit devices. As an example, the basic structure using an N-type semiconductor substrate is shown in the first example.
It is shown in the figure and explained.

A P Well diffusion layer 2 which is a P type diffusion layer is formed on an N type silicon semiconductor substrate 1, and within the region of the P Well diffusion layer 2, a source diffusion layer 3, a drain diffusion layer 4, and the source diffusion layer 3 of an N channel MOS transistor are formed. A gate insulating film 5 is provided on the surface of the P Well diffusion layer 2 between the P well diffusion layer 2 and the drain diffusion layer 4, a gate electrode 6 is provided on the gate insulating film 5, and a source electrode is connected to the source diffusion layer 3 and the drain diffusion layer 4. 7. N channel composed of drain electrode 8
On the N-type silicon semiconductor substrate 1 excluding the MOS transistor and the P well diffusion layer 2, the source diffusion layer 9 and the drain diffusion layer 10 of the P channel MOS transistor, and the silicon between the source diffusion layer 9 and the drain diffusion layer 10 are formed. A P channel consisting of a gate insulating film 11 on a semiconductor substrate 1, a gate electrode 12 disposed on the gate insulating film 11, a source electrode 13 connected to the source diffusion layer 9, and a drain electrode 14 connected to the source diffusion layer 9 and the drain diffusion layer 10. a field insulating film 15 for insulating and separating the transistor, each diffusion layer, and each electrode of the silicon semiconductor substrate 1;
The unit structure is completed.

FIG. 2 is a circuit diagram showing the configuration of a logic element, such as an inverter circuit, which is the most basic circuit configuration, obtained by appropriately connecting each of the electrodes. The relationship between Figure 1 and Figure 2 is Figure 2 Tr ₁
corresponds to the N-channel MOS transistor in FIG. 1, and Tr ₂ corresponds to the P-channel MOS transistor. Gate electrodes 6 and 12 are connected,
Drain electrode 8 of N-channel MOS becomes input
is connected to the power supply _VDD , and connects the source electrode 7 of the N-channel MOS and the drain electrode 14 of the P-channel MOS, and outputs this. The source electrode 13 of the P-channel MOS is grounded.

Both N-channel MOS and P-channel MOS are enhancement type MOS. Complementary type
The advantages of MOS include (1) low DC power consumption, and (2) high-speed operation, but the disadvantage is that P and N channel MOS transistors are formed on the same semiconductor substrate surface. In addition, since separate regions are required to electrically insulate each other, the area per unit logic is large.

As described above, an object of the present invention is to provide a semiconductor integrated circuit device that has the advantages of complementary MOS transistors and has a small element area.

A feature of the present invention is that a first source region and a first drain region of opposite conductivity type are provided on one main surface of a semiconductor substrate of one conductivity type, and a first gate insulating region is provided on one main surface between these two regions. a semiconductor film layer is provided on at least a portion of the first gate insulating film, a second gate insulating film is provided on the semiconductor film, the first gate insulating film, the second gate insulating film; The same gate electrode is provided on the semiconductor film, and extraction electrodes are provided in the first source and drain regions and at both ends of the semiconductor film.

Examples will be described in detail below with reference to the drawings.

FIG. 3 shows an embodiment of the present invention.

On the P-type silicon semiconductor substrate 21, a known MOS
An N-type source diffusion layer 22 and a drain diffusion layer 23 having the same structure are formed, and a source electrode 2 is connected to the source diffusion layer 22 and drain diffusion layer 23, respectively.
9. Field insulating film 2 with thick drain electrode 30
It is installed on 5. A first gate insulating film 24 is formed between the source diffusion layer 22 and the drain diffusion layer 23 on the surface of the silicon semiconductor substrate 21,
A P-type semiconductor film 26 is provided on at least a part of the first gate insulating film 24, and a second source electrode 31 and a second drain electrode 32 are connected to both ends of the P-type semiconductor film 26, It is placed on the thick field insulating film 25. The P-type semiconductor film 2 excluding the portion connected to the second source electrode
6 is covered with a second gate insulating film 27,
This is completed by forming a gate electrode 28 covering the first gate insulating film 24 and the second gate insulating film 27.

4A to 4F are top views of various modifications according to the present invention, respectively.

the source diffusion layer 22, the drain diffusion layer 23,
A source electrode 29, a drain electrode 30, a second source electrode 31, and a second drain electrode 32 connected to the P-type semiconductor film 26 are shown, and at the same time, the P-type semiconductor film 26 and the gate electrode 28 are shown.
The relationship between the configurations is shown as an example in FIGS. 4A to 4F.

That is, FIG. 4A shows a diagram in which the semiconductor film 26 completely covers the first gate insulating film 24 and the gate electrode 28 is installed on the first gate insulating film 24 and the second gate insulating film 27. Figure 4B
4C shows the configuration of a device having a self-alignment structure in which the first gate insulating film 24, the semiconductor film 26, the second gate insulating film 27, and the gate electrode 28 have the same width and length, and FIG. FIG. 4D shows a structure in which the width of the semiconductor film 26 is narrower than the width of the gate electrode 28, and FIG. FIG. 4E shows a further exaggerated view of FIG. 4D, which is composed of the first gate insulating film 24.
A structure for increasing the current gain of a MOS transistor is shown, and in FIG. 4F, the semiconductor film 26 is placed on a field insulating film 25 completely separated from the first gate insulating film 24. However, this fourth FF has the disadvantage that the element area becomes large.

FIG. 5 shows a wiring method when the device according to the first embodiment shown in FIG. 3 is used as an inverter. A source electrode 29 connected to the source diffusion layer 22 and a second source electrode 31 connected to the P-type semiconductor film 26 are connected as an output terminal, and a drain electrode 30 connected to the drain diffusion layer is used as a power supply terminal, The gate electrode 28 is used as an input terminal,
The second drain electrode 32 connected to the P-type semiconductor film is used as a ground terminal.

Fig. 5 is simplified, and the actual operating mechanism is shown in Fig. 6A and Fig. 7A, and the respective circuit diagrams are shown in Fig. 6A and Fig. 7A.
It is shown in Figure A and Figure 7B.

The P-type semiconductor film 26 has a thickness of 200 to 1500 Å, and the second source electrode 31 and second drain electrode 32 connected to both ends are metal films or P-type semiconductors that are in ohmic contact with the P-type semiconductor film 26. A membrane is utilized.

As shown in FIGS. 6A and 6B, the gate electrode 28
When a zero to negative voltage is applied as an input to the surface of the P-type semiconductor film 26, the silicon semiconductor plate 21
Holes are induced on the surface of the second source electrode 31, which makes ohmic contact with the P-type semiconductor film 26.
The drain electrode 32 becomes electrically conductive, but on the other hand, holes are not induced between the source diffusion layer 22 and the drain diffusion layer 23, which are N-type diffusion layers formed in the silicon semiconductor substrate 21, so that the source electrode 9 No electrical path is generated between the drain electrode 10 and the drain electrode 10. Therefore, as shown in the circuit diagram of FIG. 6B, the output shows a low level, which is a grounded state, and the power supply terminal does not consume electrical power.

On the other hand, as shown in FIGS. 7A and 7B, when a positive voltage is applied as an input to the gate electrode 28, a depletion layer 40 is formed in the P-type semiconductor film 26 in the direction of the first gate insulating film 24. The expanding depletion layer is the first
The depletion layer reaches the gate insulating film 24 and spreads also on the surface of the silicon semiconductor substrate 21, and finally an electron inversion layer is formed on the surface of the silicon semiconductor substrate 21, and the source diffusion connected to the silicon semiconductor substrate 21. The layer 22 and the drain diffusion layer 23 constitute an electrical path through the surface of the silicon semiconductor substrate 1. Therefore, the P-type semiconductor film 26 under the gate electrode 28 is occupied by a depletion layer and has high electrical resistance, and the second drain electrode 31 and the second source electrode 32 are electrically isolated. be done.

The operating mechanism is shown in the circuit diagram of FIG. 7B, where a voltage close to V _DD appears at the output terminal and becomes High level.

Despite the presence of a positive voltage at the output terminal,
Since no electrical path is generated between the source electrode 31 and the drain electrode 32 connected to the P-type semiconductor film 26, there is no DC consumption.

As described above, according to the present invention, the following effects can be expected.

(1): Low power consumption and high-speed operation are possible, which are the advantages of conventional complementary transistors.

(2): Requires less element area than conventional complementary transistors.

(3): Transistors containing semiconductor films can be expected to have a gain due to their multiple carrier operation mechanism.

In addition, although an example was shown to explain the present invention,
A similar effect can be obtained in the case of a device having an electrical conductivity type opposite to that of the above example.

The present invention is a semiconductor integrated circuit device having the feature that transistor functions of a minority carrier can be controlled using the same gate electrode.

From the above description, it is clear that according to the present invention, it is possible to obtain a semiconductor integrated circuit device with low power consumption, high speed, and small element area.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional complementary transistor, and FIG. 2 is a circuit diagram of an inverter using complementary transistors. Figure 3 shows the first embodiment of the present invention.
FIG. Figure 4 A, B, C,
D, E, and F are the second, third, and
It is a top view which shows the 4th, 5th, 6th, and 7th Example. FIG. 5 is a sectional view showing a wiring state when the first embodiment shown in FIG. 3 is used as an inverter. FIG. 6A is a schematic cross-sectional view showing a state in which a zero to negative potential is applied to the gate electrode of FIG.
FIG. 6B is a circuit diagram of this state. FIG. 7A is a schematic cross-sectional view showing a state in which a positive potential is applied to the gate electrode in FIG. 5, and FIG. 7B is a circuit diagram in this state. In the figure, 1 is a semiconductor substrate, 2 is a diffusion layer,
3 and 9 are source diffusion layers, 4 and 10 are drain diffusion layers, 5 and 11 are gate insulating films, 6 and 12 are gate electrodes, 7 and 13 are source electrodes connected to the source diffusion layers, and 8 and 14 are drain diffusion layers. 15 is a field insulating film, 21 is a P-type silicon substrate, 22 is an N-type source diffusion layer, 23 is an N-type drain diffusion layer, 24 is a first gate insulating film, and 25 is a thick field insulation film. 26 is a P-type semiconductor film, 27 is a second gate insulating film, 28 is a gate electrode, 29 is a source electrode, 30 is a drain electrode, 31 is a second source electrode, 32 is a second drain electrode, 40 is a depletion layer.

Claims (1)

[Claims] 1. A first source region and a first drain region of opposite conductivity type are provided on one main surface of a semiconductor substrate of one conductivity type, and a first gate is provided on the one main surface between the first source and drain regions. an insulating film is provided, a semiconductor film of the same conductivity type as the substrate is provided on at least a portion of the first gate insulating film, a second gate insulating film is provided on the semiconductor film, and the second gate insulating film is provided with a semiconductor film having the same conductivity type as the substrate; A gate electrode is provided on the film, and the first source region and the first
A semiconductor integrated circuit device characterized in that source and drain extraction electrodes are provided in the drain region and both ends of the semiconductor film, respectively.