JPS6276934A - Information terminal device - Google Patents

Abstract

PURPOSE:To measure a group delay without using a line monitor by obtaining the group delay from signals Q, I for eye pattern display and displaying the result. CONSTITUTION:A MODEM 21 applying PSK modulation to a reception signal and applying FSK modulation to a transmission signal outputs two kinds of signals Q, I for eye pattern display. Various controls for transmission/reception and the operation processing to reproduce a picture according to the reception signal are executed by a CPU 22. Data are transmitted or received between the CPU 22 and the MODEM 21 by a buffer 23. The display control to display the group delay of the reception signal is executed by a display control circuit 24. The signals Q, I outputted from the MODEM 21 are not converted into an analog signal but fetched in the CPU 22 while being kept as a digital signal, the group delay is calculated and the display control circuit 24 drives a display circuit 25 according to the result of calculation to display the group delay.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an information terminal device for an information transmission system using a communication line, and particularly relates to an information terminal device capable of measuring group delay of a received signal.

[Technical background of the invention]

An example of an information transmission system using a communication line is the Videotex system. This Videotex system connects an information center that stores information such as characters and figures to a receiving terminal that receives information from the information center via a telephone line, and uses this receiving terminal to respond to individual requests. It is a system that provides information to users.

In this system, it is important to know the transmission characteristics of the line at the time of installation. That is, in telephone lines and the like, as shown in FIG. 7, a group delay occurs in which the phase and amplitude of each frequency component of a transmission signal varies. In addition, the seventh
The figure shows only the phase characteristics. Therefore, in order to improve the reception rate at the receiving terminal, it is necessary to measure the group delay of the received signal at the receiving terminal and correct the group delay according to the measurement result. This correction can be performed, for example, according to the correction characteristics shown in FIG.

Methods for measuring group delay include methods such as phase slope, vibrational modulation, and frequency modulation. Another method is to measure using a line monitoring device such as an oscilloscope. This method displays an eye pattern indicating the group delay of a received signal on a cathode ray tube by sweeping a demodulated baseband signal sequence on a time axis synchronized with bits.

FIG. 9 shows a configuration for measuring group delay using a line monitor device. In FIG. 9, 11 is a receiving terminal, and terminal 12.1
3 is connected to the telephone line. This receiving terminal 1 includes a modem 111 that performs PSIC demodulation of received signals and FSIC modulation of transmitted signals, and a CP that performs various controls for transmission and reception.
It has U 112. Furthermore, this receiving terminal 1 includes S/'P conversion circuits 113 and 114 that convert two types of signals Q and I indicating the phase, etc. of the received signal outputted from the modem 111 to serial/clarel, respectively, and each S/' P converter 11
It has D/A conversion circuits 115 and 116 for digital/analog conversion of the outputs of 3 and 114, respectively. 14 is a line monitor device externally connected to the receiving terminal 11. This line monitoring device 14 includes the shame conversion circuits 115 and 116.
By sweeping two types of signals Q and I, which are output as analog signals, respectively, in the horizontal direction X and vertical direction Y, constellation observation is performed to obtain the eye pattern as described above.

FIG. 10 shows an example of an eye pattern when observing constellations. The signal sent to the receiving terminal via the telephone line is an 8-phase differential phase keying (hereinafter referred to as PSK) signal, and eight eye turns are obtained according to each phase. Since the eye pattern of each phase is shifted from the reference position on the cathode ray tube according to the group delay, the group delay can be measured by this.

[Problems with background technology]

However, the method of measuring group delay using the line monitor R14 requires a device other than the receiving terminal 1, and there is a problem in that a location for its installation must be secured.

[Purpose of the invention]

The present invention has been made to address the above-mentioned circumstances, and an object of the present invention is to provide an information terminal device that can measure group delay without using a line monitor device.

[Summary of the invention]

In order to achieve the above object, the present invention calculates group delay from signals Q and I for eye pattern display using the arithmetic processing function originally provided in the terminal, and calculates the group delay from the eye pattern display signals Q and I. Find the phase and amplitude deviation of the received signal,
This is what is displayed.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, 21 is a modem that performs PSK demodulation of received signals, FSX modulation of transmitted signals, and the like.

The modem 21 also outputs two types of signals Q and I for displaying eye patterns.

22 is a CPU that performs various controls for transmission and reception and arithmetic processing for reproducing images in accordance with received signals. 23
is a buffer that exchanges data between the CPU 22 and the modem 21. 24 is a display control circuit that performs display control to display the group delay of the received signal. 25 is a display circuit for displaying the group delay under the control of the display control circuit 24. This display circuit 25 is, for example, an LE
This is a D display circuit.

In FIG. 1, the signals Q and I output from the modem 21 are not converted into analog signals, but are sent to the CPU 2 as digital signals.
2, the group delay is calculated, and the display control circuit 24 drives the display circuit 25 according to the calculation result to display the group delay.

The outline of this embodiment has been described above, but before explaining the details of the configuration and operation of this embodiment, the received signal and the signals Q and I will now be summarized.

FIG. 2 is a circuit diagram showing the reception system of the modem 21. Second
In the figure, the signal sent through the telephone line is
It is applied to the filter 212 from the hybrid circuit 2i. This filter 212 extracts only predetermined frequency components.

This extracted output is passed through the amplifier circuit 213 to the ψ conversion circuit 21.
4 and converted to an analog signal. This analog reception signal is given to an equalizer circuit 215. Then, after being subjected to equalization processing by this equalizer circuit 215 to minimize code amount interference caused by group delay of the line,
A demodulation circuit 216 performs PSK demodulation.

In addition to the equalization process, the equalizer circuit 215 detects the level of the input signal and controls the gain of the amplifier circuit 213 according to the detection result to maintain the level of the received signal at a constant level. We also do

The output of the equalizer circuit 215 is further applied to a carrier synchronization circuit 217. This carrier synchronization circuit 217
detects the magnitude and amplitude of the received signal from the input signal and performs feedback control of the received signal according to the detection results, thereby correcting the group delay. In addition, this carrier synchronization circuit 21
7 outputs signals Q and I for eye pattern display.

The received signal is sent using the 8-phase PSK system as described above, and each phase has a meaning as shown in the table below. Further, the signal waveform is as shown in FIG. 3, for example.

The eye pattern display signals Q and I shown above are output for each phase of the received signal. In this case, the signal Q'' indicates the X component of the signal vector of each phase, and the signal line indicates the Y component. Signals Q and I are 12-bit digital signals as shown in FIG.

Next, the features of this embodiment will be explained in detail.

In FIG. 1, the 12-bit digital signals Q and I are applied as serial signals from the modem 21 to S/P conversion circuits 26 and 27, respectively. Then, in the S/P conversion circuits 26 and 27, the signal is converted into a 79 parallel signal in accordance with the clock CK output from the modem 21. This clock CK is a signal synchronized with signals Q and I as shown in FIG. Note that the S/P conversion circuit 26-21 converts only the upper eight pits of the input signal into quadrature data and discards the lower four pits in order to avoid the influence of noise and the like.

The conversion outputs of the s and ``p conversion circuits 26 and 27 are respectively latched into latch buffers 29 and 30 according to the frequency division output of the frequency division circuit 28 that divides the frequency of the clock CK.CP
U22 receives the latch output of the frequency divider circuit 28, drives the chip selector 31 according to the latch output, and f-) circuit 3.
2.33 will be opened. With this, the latch buffer 29
The latch data of ゜30 is the dart circuit 32゜33 respectively.
The data is taken into the CPU 22 through the CPU 22.

CPU J 2 calculates the group delay of the received signal from these two types of input data. CPU to obtain this group delay
FIG. 5 shows the calculation processing of No. 22. According to this figure 5, C
To explain the arithmetic processing of the PU 22, first, step S
At step 8, signals Q and I are captured. in this case,
Signals Q and I are input for each phase. However, in the Videotex system, the input order of each phase is not determined. Therefore, in the next step S, the phase angle is determined from the input data, and based on the result, the input data is divided into one of eight phases. Thereafter, the group delay of the received signal is determined for each phase. In this case, the deviation of the received phase with respect to the reference phase and the deviation of the received signal amplitude with respect to the reference amplitude are determined as the group delay.

Step S for phase deviation and amplitude deviation.

In the next Stellar fS4, the difference between both sides is combined and outputted as a group delay.

Note that FIG. 5 shows step S1. S is shown for only one phase, and it goes without saying that exactly the same processing is performed for the remaining seven phases.

Once the group delay of each phase is determined as described above, the process moves to step S, where the total group delay for eight phases is determined, and in step S6, a task is performed to convert this into output data.

The group delay data thus determined is provided to the buffer 34 via the data bus DB. After the arithmetic processing for the group delay is completed, this buffer 34 is accessed by the chip selector 3 and receives the group delay data.

This data is given to the display control circuit 24.

The display control circuit 24 is configured as shown in FIG. 6, for example. That is, the display control circuit 24 has four AND circuits 241, 242, 243°244, and the frequency dividing circuit 2
Four signals f with different frequencies output from 8
8~f4 buffer circuit 340 four output signals 81~S
4 is alternatively selected and applied to the OR circuit 245.

The buffer circuit 34 separates the degree of group delay of the received signal into five stages according to the group delay data provided from the CPU 22, and selectively outputs signals 81 to S. In this case, the output signal Sl is a signal indicating the largest group delay, and conversely, the output signal S6 is a signal indicating the smallest group delay.

For example, if the group delay is the largest, the signal S1 will be at a high level. Accordingly, the lowest frequency signal f which is output from the frequency dividing circuit 28 by dividing the frequency of the clock CK by 16
4 is selected by the AND circuit 241, and the OR circuit 245
The signal is applied to the display circuit 25 through the. As described above, the display circuit 25 is configured as an LED drive circuit, and drives the LEDs to blink in accordance with the frequency of the input signal. Similarly, signal 8
2 to S4 are output, the divided output f obtained by dividing the clock CK by 8.4.2, respectively,
,f,,f, is selected. This causes the LEDs to blink at different frequencies depending on the case. When the group delay is the smallest, the signal Ss is sent directly to the display circuit 2.
5, so the LED remains lit. In this way, in this embodiment, the degree of group delay can be determined by changing the blinking frequency of the LED depending on the degree of group delay of the received signal.

Therefore, the equalizer circuit 215 of the modem 2 can be adjusted in accordance with the degree of group delay to perform optimal group delay correction.

According to this embodiment described in detail above, since the group delay can be automatically measured inside the receiving terminal, a line monitoring device is not required. Therefore, according to this embodiment, adjustments for correcting group delay can be easily made when installing the system.

Note that the display function of the terminal may be used instead of the LED drive circuit to display the group delay.

It goes without saying that the present invention can also be applied to group delay measurements of systems other than the Videotex system.

〔Effect of the invention〕

As described above, according to the present invention, group delay can be measured without using a line monitor device.

Adjustments to correct group delay can be easily made.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of a specific configuration of a part of FIG. 1, FIGS. 3 and 4 are waveform diagrams for explaining the operation of FIG. 1, and FIG. 6 is a circuit diagram showing an example of a specific configuration of a part of FIG. 1, FIGS. 7 and 8 are characteristic diagrams for explaining group delay correction, and FIG. FIG. 9 is a block diagram showing a conventional configuration for group delay measurement, and FIG. 10 is a diagram showing a conventional display form of measurement results. 21...Modem, 22...CPU, 23.34...
- Buffer, 24...Display control circuit, 25...Display circuit, 26.27...S/'P conversion circuit, 28...
Frequency divider circuit, 29.30...Latch buffer, 31...
・Chip selector, 32.33...Date circuit. Applicant's agent Patent attorney Takehiko Suzue - 12 Dotto + Figure 4 Figure 5 C and Figure 7

Claims (1)

[Claims] In an information terminal device connected to a communication line and processing information transmitted and received via the communication line, a phase/digital signal generating a digital signal indicating the phase and amplitude of a received signal from the communication line is provided. amplitude information generating means; calculating means for calculating a deviation from a reference value of the phase and amplitude of the received signal based on the output of the phase/amplitude information generating means; and displaying the deviation according to the calculated output of the calculating means. An information terminal device equipped with a display means for displaying.