JPH11136207A - Reception signal correction system and orthogonal frequency division multiplex signal transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the problem that accurate decoding is disabled because the phase fluctuation of a received signal between symbols at a high-speed movement becomes greater than that at a low-speed movement or at a standstill and reaches ±45 degrees or over. SOLUTION: A detection circuit 313 receives received complex data, and a discrimination result outputted from a differential decoding circuit 312, detects and latches phase fluctuations at a symbol and obtains a rate of change that is a difference of the phase fluctuation between the symbol and a preceding symbol. The detection circuit 313 gives an instruction to a decoding value correction circuit 314 that the circuit 314 uses the discrimination result as it is, without changes when the rate of change is within ±45 degrees, and the detection circuit 313 selects a phase fluctuation of an adjacent signal point as the discrimination result, when the rate of change is more than ±45 degrees, and gives an instruction to the decoding value correction circuit 314 that the discrimination result is to be revised to the phase fluctuation at the adjacent signal point when a rate of change in the phase fluctuations between them is within ±45 degrees. The decoding value correction circuit 314 corrects the decoded value in accordance with the instruction of the detection circuit 313.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception signal correction system and an orthogonal frequency division multiplex signal transmission apparatus, and more particularly to a method for receiving a differential multilevel PSK modulated wave and suppressing phase and amplitude fluctuations due to the effects of fading on a transmission line. Received signal correction method to correct,
The present invention also relates to an orthogonal frequency division multiplexed signal transmission apparatus for transmitting digital information modulated by differential multi-level PSK using a plurality of carriers.

[0002]

2. Description of the Related Art In recent years, in the transmission of audio signals and video signals, digital modulation systems have been actively developed. The differential multi-level PSK (Phase Shift Keying) modulation method is a method of transmitting information by associating information with a phase difference between symbols.
On the receiving side, information can be demodulated by the delay detection method. Therefore, there is an advantage that the configuration of the demodulator is simplified as compared with the synchronous detection method.

[0003] In a receiving apparatus of a mobile communication system, the amplitude and phase of a transmission modulated wave fluctuate due to the effects of fading occurring on a transmission path. In a differential multi-level PSK modulated wave receiving apparatus, information is demodulated based on a phase difference between symbols, so that the influence of fluctuation of a received signal due to fading can be reduced.

[0004] As an example, a differential quaternary PSK modulation method for transmitting 2-bit (quaternary) information with one symbol per carrier will be described. A transmission signal has a constant amplitude and corresponds to the information to be transmitted. The four phases are represented in degrees. That is, as shown in FIG. 7, when the horizontal axis represents the signal point on the XY coordinate plane of the I axis and the vertical axis represents the Q axis, the differential four-valued PSK
The signal points of the modulation method are four at 90 ° intervals, one in each quadrant.
It is represented by two signal points. Therefore, accurate decoding is possible if the phase variation of the received signal between symbols is within ± 45 degrees.

[0005]

However, in a receiving apparatus of a mobile communication system, the phase fluctuation of a received signal between symbols during high-speed movement becomes larger than that during low-speed movement or stoppage. In this case, the phase fluctuation of the received signal becomes ± 45 degrees or more, and accurate decoding cannot be performed. In addition, when the number of values is increased to four or more, the permissible value of the phase variation becomes small, and the restriction on the moving speed becomes more severe.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a received signal correction method capable of performing accurate decoding even during high-speed movement.

Another object of the present invention is to provide an orthogonal frequency division multiplexing signal transmission apparatus for transmitting digital information subjected to differential multi-level PSK modulation on a plurality of carriers, which is suitable for use in a high-speed mobile communication system. To provide.

[0008]

In order to achieve the above object, a receiving signal correction method and an orthogonal frequency division multiplexing signal receiving side according to the present invention employ a discrete Fourier modulation method for a received differential multilevel PSK modulated wave. An arithmetic unit that converts and demodulates complex data, a differential decoding circuit that differentially decodes the complex data of the arithmetic unit, and a decoded value decoded by the differential decoding circuit and one of the signal point determination results. Received from them, detects the amount of phase variation of the received signal, calculates and calculates the rate of change of the phase variation between a plurality of symbols, and when the rate of change is smaller than a predetermined value, uses the decoded value as it is to obtain the predetermined value. In the above case, a signal point having a smaller change rate than that adjacent to the determination result is selected as a determination result, and a decoded value correction instruction signal is output.
When a detection circuit that corrects and holds the detected phase fluctuation amount to the phase fluctuation amount when an adjacent signal point is selected, receives the output decoded value of the differential decoding circuit, and receives a correction instruction signal from the detection circuit, The decoded value is corrected and output, and when no correction instruction signal is input, a decoded value correction circuit that outputs the input decoded value as it is is provided.

In the present invention, attention is paid to the continuity of the amount of phase fluctuation, and it is determined whether or not the rate of change of the amount of phase fluctuation from the previous symbol is a value larger than a predetermined value. By changing the result to an adjacent determination result, more accurate decoding can be performed.

Further, according to the present invention, the above detection circuit is provided with a first value of one of a decoded value and a signal point decoded by a differential decoding circuit.
And the first phase variation is detected and held therefrom, and when the absolute value of the phase variation is equal to or greater than a predetermined value, a second determination result adjacent to the first determination result is further obtained. Calculating and holding the second phase variation based on the decoded value is performed for at least three symbol periods, and the rate of change of the first phase variation and the rate of change of the second phase variation during that period are calculated. May be integrated into an absolute value, and an instruction signal may be output to the decoded value correction circuit so that the decoded value indicating the smaller absolute value integrated value is used as the received information.

Also in the present invention, focusing on the continuity of the amount of phase fluctuation, the rate of change of the amount of phase fluctuation is integrated as an absolute value, and the decoded value indicating the smaller absolute value integrated value is used as the received information. Decoding.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a received signal correction system according to the present invention. This embodiment also constitutes a DFT and differential QPSK decoding circuit 31 in an orthogonal frequency division multiplexed signal receiving device described later. Here, an orthogonal frequency division multiplexing signal (OFDM signal) for transmitting and receiving transmission information using 257 carriers will be described as an example. This OFDM signal has 512 points of I
It is a signal generated by performing a DFT (Inverse Discrete Fourier Transform) operation, and applies 2-bit information to one carrier wave by differential Q (quaternary) PSK modulation. In addition, a reference signal (reference data), a pilot signal, and the like are inserted into one symbol using nine carriers in addition to the transmission information of 248 carriers.

In FIG. 1, a differential QPSK decoding circuit 31
Is composed of a DFT operation unit 311, a differential decoding circuit 312, a detection circuit 313, and a decoded value correction circuit 314. The received OFDM signal is demodulated and digitized, the guard interval period is removed, and the in-phase (I)
After being converted into a signal and a quadrature (Q) signal, they are supplied to the DFT operation unit 311 and converted into reception complex data. Conventionally, the received complex data is determined to be any one of four signal points ± 1 ± j, and then converted into transmission information by differential decoding which is the reverse of the transmission side.

On the other hand, in this embodiment, the received complex data is supplied to a differential decoding circuit 312, where it is determined to be any one of ± 1 ± j, and then supplied to a decoded value correction circuit 314. With the received complex data (decoded value) and the signal point ±
The result determined as any one of 1 ± j is supplied to the detection circuit 313. The detection circuit 313 receives the received complex data output from the differential decoding circuit 312 and the determination result, detects and holds the amount of phase variation in the symbol (n). An example of the phase fluctuation is an amount corresponding to a (n) shown in FIG. The horizontal axis shown in FIG. 2 is the real axis and the vertical axis is the imaginary axis 2
In the dimensional coordinate plane, the phase variation a (n) is an angle between the vector A of the received complex data and the vector B of the determination result (here, + 1 + j).

Next, the detection circuit 313 calculates a change rate A (n) = the difference from the phase fluctuation amount a (n−1) in the previous symbol.
a (n) -a (n-1) is obtained. The change rate A (n) is ±
If it is within 45 degrees, the determination result is left as it is.
On the other hand, if the change rate A (n) is a value larger than ± 45 degrees, the detection circuit 313 selects an adjacent signal point as a determination result, and the change rate A ′ with the phase fluctuation amount of the changed determination result.
If (n) is within ± 45 degrees, it instructs the decoded value correction circuit 314 to change the determination result to the adjacent signal point. The detection circuit 313 holds the phase fluctuation amount at that time.

As a simple example, a state in which the phase axis changes counterclockwise, that is, the phase fluctuation is 1 for each symbol
These operations will be briefly described in a state where the angles are changed to 0 degree, 30 degrees, and 50 degrees. The transmitting side sends + 1 + j three times, and sets the counterclockwise direction as the positive direction. Now, as shown in FIG. 3A for a certain symbol, the determination result is + 1 + j
And the phase variation a (n−2) with the received complex data I is +
Assuming that it is 10 degrees, the next symbol
As shown in (B), the determination result is + 1 + j, the phase variation a (n-1) with the received complex data II is +30 degrees, and the change rate A (n-1) is 20 degrees (= a). (N-
1) -a (n-2) = 30 degrees-10 degrees). Since the change rate A (n-1) is within ± 45 degrees, the determination result is left as it is.

In the next symbol, as shown in FIG. 3C, assuming that the determination result is -1 + j and the phase variation a (n) with the received complex data III is -40 degrees, the change rate A (N) is -70 degrees (= a (n) -a (n-1) =-
40 degrees-30 degrees). The rate of change A (n) is ± 45
If the determination result is changed to the adjacent signal point + 1 + j as shown in FIG. 3D, the phase variation a ′ (n) with the received complex data III becomes 50 degrees (= 90 degrees).
Degrees−40 degrees), and the change rate A ′ (n) is 20 (= a ′).
(N) -a (n-1) = 50 degrees-30 degrees). Therefore, since the corrected determination result is more likely, the detection circuit 313 holds the phase variation amount as a ′ (n) = 50 degrees and instructs the decoded value correction circuit 314 to correct the determination result.

The decoded value correction circuit 314 shown in FIG. 1 receives the judgment result from the differential decoding circuit 312,
Correct the decrypted value according to the instruction of 3. Further, the decoded value correction circuit 314 converts the information into transmission information by differential decoding which is the reverse of the transmission side, and outputs the transmission information.

As described above, according to this embodiment, it is determined whether or not the rate of change of the amount of phase fluctuation with respect to the previous symbol is greater than ± 45 degrees by focusing on the continuity of the phase fluctuation.
When the rate of change is greater than 45 degrees, more accurate decoding can be performed by changing the determination result to an adjacent signal point, and thus it is suitable for application to a receiving device that moves at high speed.

Next, another embodiment of the present invention will be described. In this embodiment, depending on the direction of the phase fluctuation,
The determination result in the detection circuit 313 is branched into several branches. For example, when the received complex data indicated by a black circle in FIG. 6 is obtained, the judgment result of + 1 + j is most likely. However, as shown in FIG. 6, when the phase fluctuation amount with respect to the judgment result of + 1 + j is large in the positive direction, −1 + j is obtained. There could be. Therefore, in this embodiment, when the absolute value of the phase variation is larger than a predetermined value, the phase variation with the determination result of the next possible adjacent signal point is obtained as a branch.
The rate of change is calculated for each branch and the absolute value is integrated for each branch over the symbol period or longer, and the decoded value of the branch indicating the smaller absolute value integrated value is used as reception information.

That is, when the phase variation is larger than +30 degrees, for example, the phase variation in the determination result (signal point) and the phase variation in the determination result of the next possible adjacent signal point are determined. Is calculated as a branch. That is, when the determination result is + 1 + j, the phase variation amount when the determination result is -1 + j is branched, and similarly, when the determination result is + 1-j, the phase variation amount when the determination result is + 1 + j When the judgment result is −1−j, the phase variation amount when the judgment result is + 1−j is −1.
In the case of + j, the phase variation amount when the judgment result is −1−j is branched as a branch.

When the phase variation is +30 degrees or less and -30 degrees or more, that is, when the absolute value of the phase variation is 30 degrees or less, the phase variation is small and the determination result is used as it is. If the phase variation is smaller than −30 degrees (large in the negative direction), the phase variation in the next possible determination result is calculated together with the determination result. That is,
When the judgment result is + 1 + j, the phase fluctuation amount when the judgment result is + 1-j is branched, and similarly, when the judgment result is -1 + j, the phase fluctuation amount when the judgment result is + 1 + j is When the judgment result is −1−j, the phase fluctuation amount when the judgment result is −1 + j, and the judgment result is −1−j
In the case of j, the phase variation amount when the determination result is −1−j is branched as a branch.

The receiving side holds the phase variation amounts of these branched branches up to a predetermined value of three symbol periods or more, and performs an integration operation of the absolute value of the change rate of each branch. The determination result of the branch showing the small absolute value integrated value is regarded as the reception information. This function is performed by the detection circuit 313.

Next, still another embodiment of the present invention will be described. In the OFDM signal transmission method, which is a multicarrier transmission method, adjacent carriers have characteristics similar to phase fluctuations, which are transmission path characteristics. for that reason,
The amount of phase fluctuation can be averaged for several carriers to remove noise, and a highly reliable phase fluctuation can be obtained. The same applies to the time axis direction.

Next, an embodiment of the orthogonal frequency division multiplex signal transmission apparatus of the present invention will be described. FIG. 4 shows a block diagram of an embodiment of the transmission apparatus of the orthogonal frequency division multiplex signal transmission apparatus according to the present invention. In FIG. 1, digital data to be transmitted is input to an input terminal 1. The digital data is, for example, a digital video signal or an audio signal compressed by an encoding method such as an MPEG method which is a color moving image encoding and displaying method.

The input digital data is supplied to an input circuit 2 including a differential encoding circuit, and if necessary, an error correction code is applied based on a clock from a clock frequency divider 3. The information to be transmitted is allocated to each carrier by 2 bits at a time by the dynamic encoding circuit, and is converted into complex data of ± 1 ± j. The clock divider 3 divides an intermediate frequency of 10.7 MHz from the intermediate frequency oscillator 10 and generates a clock synchronized with the intermediate frequency.

The complex data from the input circuit 2 is supplied to a calculation unit 4 and is generated as an in-phase signal (I signal) and a quadrature signal (Q signal) on a time axis by an inverse discrete Fourier transform (IDFT) calculation. Each is supplied to a predetermined input terminal and subjected to IDFT operation. The symbol number counting circuit 5 outputs 0, 1, 2, 3,. . . , 254, 25
5,0,1,2,. . . A symbol number which is sequentially and cyclically increased is supplied to the reference signal insertion circuit 6, and is also supplied to the arithmetic unit 4 so that the symbol number is assigned to a specific carrier (for example, the first carrier). insert.

Further, the reference signal inserting circuit 6, may leak with inserting a reference signal as a known reference data to data transmitted at a certain carrier frequency + W _n, the error of the orthogonal as an image component or crosstalk Also, known reference data is inserted into data having a negative carrier frequency −W _n symmetrical with respect to the center carrier frequency F0. The carrier frequency at which the reference signal is inserted and transmitted is determined in advance in association with the symbol number, and is switched at regular intervals. This is because transmission characteristics are often different for each frequency.

For example, as for the reference signal (reference data), a predetermined value p _S is set only for the real part of the complex number transmitted at the positive carrier frequency + W _n (as the first set) for even symbols, and the others are set to zero, and the odd numbers are set. In the symbol, a predetermined value r _S is set only for the real part of the complex number transmitted as a symmetric negative carrier frequency −W _n (as the second set), and the others are set to zero.

As an example, the arithmetic unit 4 has a data sequence N of 25.
When transmitted on six carriers, a signal is generated by performing IDFT operation of double oversampling. At this time, the input assignment to the arithmetic unit 4 is as follows when the numbers are sequentially assigned in the input frequency alignment type.

[0031]

[Outside 1] That is, the number of input terminals of the arithmetic unit 4 is 511 for the real part (R) signal and 511 for the imaginary part (I) signal, respectively.
There are 512 to the first, of which the first (n = 1)
To the 127th (n = 127) from the 385th (n = 385) to the 511th (n = 5)
11) Information signals are input to a total of 127 input terminals, a DC voltage (constant) is input to a 0th (n = 0) input terminal, and a 128th (n = M / 4) is input. 38
For example, a fixed voltage for a pilot signal is input to the fourth (n = 3M / 4) input terminal.

The operation unit 4 thus obtains 127 from the first
A 4-bit R signal and a 4-bit I signal are input to the input terminal and the 385th to 511th input terminals, respectively, and a constant voltage is input to the 0th, 128th and 384th input terminals. After that, 0 is input to the 129th to 383rd input terminals, and a double oversampling IDFT operation is performed. As a result, an in-phase signal (I signal) and a quadrature signal (Q signal) are obtained. I
After inserting a guard interval for reducing multipath distortion into the signal and the Q signal, the signal and the Q signal are output to the output buffer 7.

Here, a total of 1 from the 1st to the 128th
The input information of the 28 input terminals is a carrier for information transmission on the upper side (higher frequency side) with respect to the center carrier frequency F0 transmitting the input information of the 0th input terminal (this is referred to as a positive carrier or a positive carrier in this specification). Carrier).
The input information of a total of 128 input terminals from the 384th to the 511th is a carrier for information transmission lower (lower side) with respect to the center carrier frequency F0 (this carrier is referred to as a negative carrier or carrier in this specification). ), Especially 1
As a result of the IDFT operation, the input pilot signals of the 28th and 384th input terminals are transmitted on carrier waves at both ends of the frequency, which is equivalent to half the Nyquist frequency,
0 is input to the remaining 129th to 383th input terminals (the ground potential), so that a carrier wave of that portion is not generated (not used for data transmission).

In the output buffer 7, the output operation result of the operation unit 4 is generated in a single IDFT operation, and 256 pieces of input information are generated in bursts as 512 time-axis signals (I signal and Q signal). On the other hand, since the circuits subsequent to the output buffer 7 operate continuously at a constant reading speed of the content of the output buffer 7, they are provided to adjust the time difference between the two.

Based on the clock from the clock divider 3 in FIG. 1, I
The I and Q signals resulting from the DFT operation are supplied to a D / A converter / low-pass filter (LPF) 8, where they are converted into analog signals using the clock from the clock divider 3 as a sampling clock. , LPF pass the necessary I-band and Q-band components of the baseband frequency band components and supply them to the quadrature modulator 9.

The quadrature modulator 9 has an intermediate frequency of 10.7 MHz from the intermediate frequency oscillator 10 and a 10.7 MHz phase shifted by 90 ° by the 90 ° shifter 11.
MHz intermediate frequency as each carrier, and D
The quadrature modulation is performed on the baseband frequency band component I signal and Q signal input from the / A converter / LPF 8 to perform an intermediate frequency band (IF signal band) and differential quaternary PSK modulation (QPSK). An OFDM signal composed of 257 information carriers (128 pairs of positive and negative carriers and one central carrier) is generated. The OFDM signal output from the quadrature modulator 9 is converted by the frequency converter 12 into RF in a predetermined transmission frequency band.
After being frequency-converted into a signal, the signal is subjected to transmission processing such as power amplification in the transmission unit 13 and radiated from an antenna (not shown).

FIG. 5 is a block diagram showing an embodiment of a receiving apparatus on the receiving side of the orthogonal frequency division multiplexing signal transmission apparatus according to the present invention. In FIG. 5, the above-mentioned 248 information carrier waves, which are differentially QPSK-modulated so as to transmit 2 bits of information per symbol input through a spatial transmission path, and nine other information carrier waves, OF
The DM signal is received by a receiving unit 21 via a receiving antenna, is then subjected to high-frequency amplification, is further frequency-converted to an intermediate frequency by a frequency converter 22, is amplified by an intermediate-frequency amplifier 23, and is then subjected to carrier extraction having a configuration to be described later. And a quadrature demodulator 24.

The carrier extraction circuit portion of the carrier extraction and quadrature demodulator 24 is a circuit for extracting the center carrier (carrier) of the input OFDM signal as accurately as possible with a small phase error. Here, each carrier for transmitting information is placed adjacent to every 387 Hz that is a symbol frequency and OFD
Since the M signal is formed, the carrier for information transmission adjacent to the center carrier is also separated by 387 Hz from the center frequency, and in order to extract the center carrier, the carrier for information transmission adjacent to the carrier only 387 Hz is separated. A highly selective circuit is used so as not to be affected.

The center carrier F0 extracted by the carrier extraction and quadrature demodulator 24 is supplied to the intermediate frequency oscillator 25, where it is synchronized with the center carrier F0 by 10.7.
Generate an intermediate frequency of MHz. Intermediate frequency oscillator 2
5 is directly supplied to the quadrature demodulator 24 as the first demodulation carrier, while the phase is shifted by 90 ° by the 90 ° shifter 26, and then the carrier extraction and quadrature demodulation are performed as the second demodulation carrier. Is supplied to the vessel 24.

As a result, an analog signal (frequency division multiplexed signal) equivalent to the analog signal input to the quadrature modulator 9 of the transmitting apparatus is demodulated and extracted from the carrier extraction and quadrature demodulator section of the quadrature demodulator 24. , A low-pass filter (LPF) 28
, A signal of a required frequency band transmitted as OFDM signal information is passed, supplied to an A / D converter 29, and converted into a digital signal.

The sampling timing for the input signal of the A / D converter 29 is generated based on a sample synchronization signal having a frequency twice the Nyquist frequency, which is generated from the pilot signal by the synchronization signal generation circuit 27. That is, the pilot signal is set at a predetermined integer ratio with respect to the sample clock frequency, and the frequency of the pilot signal is multiplied according to the frequency ratio to obtain the timing of the sample clock.

The synchronizing signal generation circuit 27 receives the demodulated analog signal and generates a sample synchronizing signal by a PLL circuit which performs phase synchronization with a pilot signal transmitted as a continuous signal in each symbol period including a guard interval period. A generating circuit section, a symbol synchronization signal generating circuit section for examining a phase state of a pilot signal based on a signal extracted from a part of the sample synchronization signal generation circuit section, detecting a symbol period, and generating a symbol synchronization signal; A system clock generating circuit for generating a system clock such as a section signal for removing a guard interval period from the signal and the symbol synchronization signal.

The digital signal extracted from the A / D converter 29 is supplied to a guard interval period processing circuit 30, where the digital signal is less affected by multipath distortion based on the system clock from the synchronization signal generation circuit 27. DFT, differential QPSK decoding circuit 3
1 is supplied.

The DFT / differential QPSK decoding circuit 31 has the same configuration as the block diagram shown in FIG. 1, and the original digital information is decoded by the DFT operation and the differential decoding by the method described above. The decoded digital information signal is subjected to output processing such as parallel-serial conversion by the output circuit 32 of FIG.

In such an orthogonal frequency division multiplexed signal receiving apparatus, the operation of the detection circuit 313 in the DFT / differential QPSK decoding circuit 31 can be applied to any of the above embodiments. As a result, even when the present invention is applied to a receiving device that moves at a high speed, more accurate decoding can be performed as compared with the related art.

The present invention relates to the differential 4 of the above embodiment.
The present invention is not limited to the value PSK modulation.
The K modulation includes differential 8-level PSK modulation and other π / 4 shift QPSK modulation, and furthermore, multi-level QAM.
It is also applicable in modulation.

[0047]

As described above, according to the present invention,
Focusing on the continuity of the amount of phase variation, the absolute value of the rate of change of the amount of phase variation is integrated into absolute values, and a decoded value indicating a smaller absolute value integrated value is used as reception information, so that more accurate decoding can be performed. Error-free differential multi-value PS even at high speeds
It is possible to decode K modulated waves. Further, according to the present invention, when applied to an OFDM signal transmission apparatus in which each carrier is subjected to differential multi-level PSK modulation, it is possible to improve the demodulation performance when the receiving apparatus moves at high speed due to the above effects. .

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a decoding circuit of a main part of a reception signal correction system and an orthogonal frequency division multiplex signal transmission apparatus of the present invention.

FIG. 2 is a diagram illustrating an example of phase fluctuation.

FIG. 3 is a diagram for explaining a decoded value correction operation in the embodiment of FIG. 1;

FIG. 4 is a block diagram of an embodiment of a transmitting apparatus of the orthogonal frequency division multiplexing signal transmission apparatus according to the present invention.

FIG. 5 is a block diagram of an embodiment of a receiving side device of the orthogonal frequency division multiplexing signal transmission device according to the present invention.

FIG. 6 is a diagram illustrating an example of a signal point arrangement of a decoded signal.

FIG. 7 is a signal point arrangement diagram of a 4-level PSK modulation method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 digital data input terminal 2 input circuit including differential encoding circuit 3 clock divider 4 arithmetic unit 5 symbol number coefficient circuit 6 reference signal insertion circuit 7 output buffer 9 quadrature modulator 10, 25 intermediate frequency oscillator 13 transmission unit 21 Receiving unit 24 Carrier extraction and quadrature demodulator 27 Synchronous signal generation circuit 30 Guard interval period processing circuit 31 DFT, differential QPSK decoding circuit 311 DFT calculation unit 312 Differential decoding circuit 313 Detection circuit 314 Decoding value correction circuit

Claims (5)

[Claims] An arithmetic unit for demodulating complex data by discrete Fourier transforming the received differential multilevel PSK modulated wave; a differential decoding circuit for differentially decoding the complex data of the arithmetic unit; Receives the decoded value decoded by the differential decoding circuit and the decision result of any one of the signal points, detects the phase variation of the received signal from them, and calculates the rate of change of the phase variation between a plurality of symbols. When the change rate is smaller than a predetermined value, the decoded value is used as it is. When the change rate is equal to or larger than the predetermined value, a signal point adjacent to the judgment result with a smaller change rate is selected as the judgment result and the decoded value is selected. A detection circuit that outputs a correction instruction signal, corrects and holds the detected phase fluctuation amount to a phase fluctuation amount when the adjacent signal point is selected, and receives an output decoded value of the differential decoding circuit, The correction instruction from the detection circuit A decoded value correction circuit for correcting a decoded value when a signal is input and outputting the decoded value, and outputting an input decoded value as it is when the correction instruction signal is not input. 2. The detection circuit receives a decoded value decoded by the differential decoding circuit and a first determination result of any one of signal points, and detects and holds a first phase fluctuation amount from them. At the same time, when the absolute value of the phase variation is equal to or greater than a predetermined value, a second phase variation is further calculated based on the second determination result of the signal point adjacent to the first determination result and the decoded value. Is performed for at least three symbol periods, and the rate of change of the first phase variation and the rate of change of the second phase variation during that period are integrated as absolute values to obtain a smaller absolute value. 2. The received signal correction method according to claim 1, wherein an instruction signal is output to the decoded value correction circuit so that the decoded value indicating the value integrated value is used as reception information. 3. A transmitting apparatus for generating and outputting an orthogonal frequency division multiplex signal in which each of a plurality of frequency-divided carrier waves is subjected to differential multi-level PSK modulation; Value PSK
Receiving means for obtaining a modulated wave; an arithmetic unit for demodulating complex data by performing discrete Fourier transform on the differential multi-level PSK modulated wave from the receiving means; and differentially decoding the complex data of the arithmetic unit A differential decoding circuit, receives a decoded value decoded by the differential decoding circuit and one of the signal point determination results, detects a phase variation amount of the received signal based on the received value, and detects a plurality of the phase variations. When the change rate between symbols is calculated and calculated, the decoded value is used as it is when the change rate is smaller than a predetermined value, and when the change rate is equal to or larger than the predetermined value, a signal point having a smaller change rate than the signal point adjacent to the determination result is determined. A detection circuit that outputs a correction instruction signal of a decoded value selected as a determination result, and corrects and holds the detected phase fluctuation amount to a phase fluctuation amount when the adjacent signal point is selected; and the differential decoding circuit. Receiving the output decrypted value of And a decoded value correction circuit that corrects and outputs a decoded value when the correction instruction signal is input from the detection circuit, and outputs an input decoded value as it is when the correction instruction signal is not input. Orthogonal frequency division multiplexing signal transmission apparatus. 4. The detection circuit receives a decoded value decoded by the differential decoding circuit and a first determination result of any one of signal points, and detects and holds a first phase fluctuation amount therefrom. When the absolute value of the phase variation is equal to or more than a predetermined value, a second phase variation is further calculated based on a second determination result, which is a signal point adjacent to the first determination result, and the decoded value. Is performed for at least three symbol periods, and the rate of change of the first phase variation and the rate of change of the second phase variation during that period are integrated in absolute values to obtain a smaller value. 4. The orthogonal frequency division multiplexed signal transmission apparatus according to claim 3, wherein an instruction signal is output to the decoded value correcting circuit so that the decoded value indicating the absolute value integrated value becomes reception information. 5. The detection circuit according to claim 1, wherein the detection circuit averages a detected phase variation amount based on decoded values of a plurality of adjacent carriers of the received orthogonal frequency division multiplexed signal, and converts the average value into decoded values of the plurality of carriers. 5. The orthogonal frequency division multiplexed signal transmission device according to claim 3, further comprising means for setting a corresponding phase fluctuation amount.