JPS6276552A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a planar type hetero-junction bipolar-transistor, and to change a semiconductor device easily into an integrated circuit by providing a reverse conduction type base formed by introducing reverse conduction type impurity ions between specific emitter and collector. CONSTITUTION:Si ions are implanted to form an Si introducing region 3A for a collector, Al ions and Si ions are implanted to shape Al and Si introducing regions 6A for an emitter, an silicon nitride film 7 is formed, and Mg ions are implanted to shape a Mg introducing region 8A for a base. A heat-treatment protective film 9 consisting of aluminum nitride is shaped, and the whole is thermally treated through lamp-annealing, and dipped into a hot phosphoric acid etching liquid to remove the heat-treatment protective film 9, thus forming a base electrode 10. A collector-electrode contact window and an emitter- electrode contact window are formed, an AuGe/Au film is shaped, a collector electrode 11 and an emitter electrode 12 are formed through patterning, and an each electrode is brought to ohmic properties through alloying and heat treatment.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a compound semiconductor device consisting of a heterojunction bipolar transistor, which has a collector made of a compound semiconductor layer (or substrate) of one conductivity type, and a case where the collector is introduced into the collector. formed by ion implantation of atoms that combine with the compound semiconductor constituting the one conductivity type semiconductor layer (or substrate) to produce a compound semiconductor having a larger energy band gap than that of the compound semiconductor, and are of the same conductivity type as the collector. A planar type that can be easily integrated into a circuit by adopting a configuration including an emitter of the type and a base of an opposite conductivity type formed by introducing impurity ions of an opposite conductivity type between the emitter and the collector. It was made possible to achieve this goal.

[Industrial application field]

The present invention relates to a compound semiconductor device composed of a Brehner-type heterojunction bipolar transistor.

[Conventional technology]

In recent years, thin semiconductor layers have been stacked to form heterojunctions,
There is active research and development into bipolar transistors that allow current to flow in the vertical direction, and this type of transistor is
Large current drive capability, ie transfer conductance g. Since it is large, the time to charge and discharge the load capacitance is short, and therefore it is advantageous not only to increase the speed of the transistor itself but also to increase the speed of the entire electronic device.

(Problems to be Solved by the Invention) In the vertical heterojunction bipolar transistor, if the emitter is formed on the front side, it is easy to take out the electrode from there, but it is difficult to take out the electrode from the collector or base. performs step-like mesa etching to expose part of the surface of the collector layer and base layer, and electrodes are formed there.

Transistors with such stepped mesas have various problems when integrated into integrated circuits due to their complicated shape and the presence of large steps, making it difficult to form electrodes and wiring. .

The present invention provides a Brehner-type heterojunction bipolar transistor that can be easily integrated into an integrated circuit.

Means for solving problem C] Diagram (A) for explaining the process of manufacturing an embodiment of the present invention
This will be explained using (E).

The compound semiconductor device of the present invention includes a collector made of a compound semiconductor layer of one conductivity type (e.g., n-type GaAs collector region 3), and a compound semiconductor (e.g., GaAs) that constitutes the semiconductor layer of one conductivity type when introduced into the collector. ) is formed by ion implantation of atoms (e.g., Aj2) that combine with the collector to form a compound semiconductor (e.g., AIGaAs) with a larger energy band gap than that of the semiconductor, and is of the same conductivity type as the collector (e.g., n-type). An emitter of an opposite conductivity type (for example, Mg) is formed by introducing impurity ions of an opposite conductivity type (for example, Mg) between the emitter and the collector.
For example, the configuration includes a p-type (p-type) base.

[Effect]

By using the above method, the heterojunction bipolar transistor becomes a planar type, so when it is integrated into a compound semiconductor device, it is difficult to form a stepped mesa or to form electrodes and wiring in large steps. This will eliminate the problem and make it easier to obtain highly reliable products.

〔Example〕

Figures (A) to (E) are cross-sectional side views of essential parts of a compound semiconductor device at key points in the process for explaining the manufacturing of an embodiment of the present invention, and these figures will be referred to below. I will explain.

See Figure (A) (al) By applying the resist process in normal photolithography technology, semi-insulating Ga
A photoresist film 2 having an opening 2A is formed on an As substrate 1.

(b) By applying the ion implantation method, Si ions are implanted to form the collector Si introduction region 3A.

The ion implantation conditions in this case are: Impurity amount: I x 10'2 (am-3:1 acceleration energy: 100 (KeV)) See Figure (B) (C1 chemical vapor deposition).

A silicon dioxide (Si02) film 4 having a thickness of approximately 5000 nm is grown by applying the ur deposition (CVD) method.

(dl By applying a normal photolithography technique, the SiO2 film 4 is patterned using the photoresist film 5 having the opening 5A as a mask to form the opening 4A.

When forming this opening 4A, a slight side etching is performed to form a so-called stencil structure in which the photoresist film 5 overhangs. In this case, the amount of side etching is selected to be approximately 7000 cm.

+e) By applying the ion implantation method, Al ions and Si ions are implanted to form emitter A1 and Si introduced region 6A.

The ion implantation conditions in this case are: For Al ions, dose: 5 x 1016 (cm-") Acceleration energy: 130 (KeV) For Si ions, impurity amount: I x 10"(cm-") Acceleration energy: 130 (KeV).The purpose of introducing 1.l is to generate a compound with GaAs and form an emitter region made of Aj'GaAs, which has a larger energy band gap than Q a As. Also, the reason why Si is introduced is that the impurity concentration in the emitter region needs to be higher than that in the collector region.

See Figure (C) (by applying reactive sputtering with the photoresist film 5 used when buttering the flsi02 film 4 intact, silicon nitride with a thickness of about 5,000 mm) was formed. A (S i 3N4) film 7 is formed.

As explained above, the photoresist film 5 is
Since the 3i3N4 film 7 formed in this step overhangs the 2 film 4, the 3i3N4 film 7 formed in this step
Although it penetrates under the hung photoresist film 5, it does not come into contact with the 5i02 film 4, and a gap 7A of about 3,000 cm, for example, is created between it and the 5i02 film 4.

(By applying the gl ion implantation method, Mg ions are implanted, and the base Mg 'X human area 8
Form A.

The ion implantation conditions in this case are: Impurity amount: lX10” (low 3) Acceleration energy: 150 (KeV) It is.

At this time, an Mg introduced region 8B is also formed on the other side of the emitter A1 and the Si introduced region 6A, but this region does not interfere with the operation of the transistor.

In order to prevent the Mg introduction region 8B from being formed, Mg ions may be implanted after forming a mask that fills the corresponding gap 7A.

See figure (D) (h) By applying the reactive suba-7ta method,
For example, a heat-treated protective film 9 made of aluminum nitride (ANN) is formed to a thickness of about 1000 cm.

(1) By applying the lamp annealing method,
Perform heat treatment.

The heat treatment conditions at this time are as follows: Light source: tungsten halogen lamp Temperature: 950[
"C) Irradiation time = 6 [seconds]. Through this heat treatment, the collector Si introduction region 3
A, Al and Si introduction region 6A for emitter, M for base
The impurity concentration of the g4-person region 8A is approximately I x 1016 (
n-type QaAs collector region 3 with an impurity concentration of about 3×10” (cm-’), and n-type A with an impurity concentration of about 3×10” (cm-’)
The IGaAs emitter region 6 has an impurity concentration of about 5 x 10''(Cm-') and a thickness of about 3 cm.
000 C] p-type GaAs base region 8
is converted to

See Figure (E) fJl The heat-treated protective film 9 is removed by immersion in a hot phosphoric acid etching solution.

(k) A u Z n / by applying the vacuum evaporation method
The base electrode 10 is formed by growing an Au film to a thickness of about 500/3000 mm and patterning it by applying an ion milling method.

(1) By applying a normal photolithography technique, the S i O 2 film 4 and the S i 3 N 47 are patterned to form a collector electrode contact window and an emitter electrode contact window.

(m) While leaving the photoresist film that was used as a mask when patterning the 5i02 film 4 and the Si3N4 film 7, a vacuum evaporation method was applied to form an AuGe/Au film with a thickness of about 20 mm.
0/3000 C people].

Buttering the A u G e / A u film by applying a lift-off method to dissolve and remove (nl the photoresist film that is the mask),
A collector electrode 11 and an emitter electrode 12 are formed.

(0) Alloying heat treatment is performed at a temperature of 450 ("C) and a time of 30 [seconds] to make each electrode ohmic.

It goes without saying that the compound semiconductor device produced in this way is of the Brenna type as seen from the figure, and therefore there is no difficulty in manufacturing it even if it is integrated into an integrated circuit.

〔Effect of the invention〕

The compound semiconductor device according to the present invention includes a collector made of a compound semiconductor layer (or substrate) of one conductivity type, and a compound semiconductor that forms the compound semiconductor layer (or substrate) of one conductivity type when introduced into the collector. and an emitter formed by ion implantation of atoms that produce a compound semiconductor with a larger energy band gap and having the same conductivity type as the collector, and an impurity of an opposite conductivity type between the emitter and the collector. The structure includes a base of opposite conductivity type formed by introducing ions.

According to this configuration, the heterojunction bipolar transistor is a planar type in which current flows in the horizontal direction, so when integrating them into an integrated circuit, it is difficult to form a complex step-like mesa or have large steps. Manufacturing difficulties such as forming electrodes and wiring with this in mind are completely eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. (A) to (E) are cross-sectional side views of essential parts of a compound semiconductor device at key points in the process for explaining the manufacturing of an embodiment of the present invention. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a photo substrate.
Resist film, 3 is n-type GaAs collector region, 4 is 5i
02 film, 5 is photoresist film, 6 is n-type AlGaA
s emitter region, 7 is Si3N4 film, 8 is p-type GaAs
a base region, 9 a heat-treated protective film, 10 a base electrode, 1
1 indicates a collector electrode, and 12 indicates an emitter electrode. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Shoji Aitani Representative Patent Attorney Hiroshi Watanabe - (A) (B) (C) (D) (E) Illustration procedure main document explaining the manufacturing process (method) ) % formula % 1 Indication of the case 1985 Patent Office No. 114313 2 Title of the invention Compound semiconductor device 3 Relationship to the amended person case Patent applicant address 1015 Kamikokyunaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name (522) Fujitsu Limited Representative Takashi Yamaki 4 Agent address 20-7, Toranomon-chome, Minato-ku, Tokyo Drafting date: September 3, 1985 Shipping date: September 30, 1988 6 Amendment Target: A column for a brief explanation of the detailed drawing. drawing. il+ Specification page 12, line 6, ``The description of Figure J,
"Figure 1", corrected as follows. ! 2) Original drawings of 19Jl (Figures (A, ) to (
E)) are attached and replaced with the attached page (Fig. 1 (A) to (E)). 8 Inventory drawings of attached documents (Figure 1 (A) to (E)) Series (A) Figure 1 (B) Figure 1 (C) Figure 1 (D), 7 (E) Explaining the manufacturing process figure

Claims (1)

[Scope of Claims] A collector consisting of a compound semiconductor layer (or substrate) of one conductivity type, and a compound semiconductor that, when introduced into the collector, combines with the compound semiconductor constituting the compound semiconductor layer (or substrate) of one conductivity type, and then an emitter formed by ion implantation of atoms that produce a compound semiconductor with a large energy band gap and having the same conductivity type as the collector; and introducing impurity ions of an opposite conductivity type between the emitter and the collector. What is claimed is: 1. A compound semiconductor device comprising: a base of opposite conductivity type formed as a compound semiconductor device;