JPS6275866A - Transfer control system - Google Patents

Abstract

PURPOSE:To attain the transfer of data with priority and also with no priority without having a long waiting time by arranging the registers on two stages at the side of the highest priority and making the registers set on the rear stage accept data by the AND conditions between the output of the front stage side and the scan end information on the rear stage side. CONSTITUTION:A scan circuit 6 first checks the presence or absence of acceptance for transfer request with a register 3b and then connects a processor 1 at the priority side to a processor 8 via a switching circuit for transfer of data with the processor 1 if the acceptance of the transfer request is confirmed. While the circuit 6 transmits the gate signal to an AND gate 5 when no acceptance is confirmed. The acceptance transfer request of a register 3a is taken over by a register 3b by said gate signal. Then the acceptance of a transfer request is checked with a register 4. When this acceptance is confirmed, a processor 2 is connected to the processor 8 via the circuit 7 for transfer of data with the processor 2 only when the output of the register 3b is delivered in a period corresponding to a break of the processor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a transfer control method for controlling competing operations of data transfer requests from two types of processing devices.

[Background of the invention]

Regarding a method for controlling competing operations of access requests from two types of processing devices, for example, Japanese Patent Laid-Open No. 53-72532
Publication No. In this example, a method is adopted in which the access request signal is delayed for access from the non-priority side. This method is effective only when two types of access requests occur simultaneously, and is ineffective against access requests that occur randomly.

[Purpose of the invention]

An object of the present invention is to provide a transfer control method that allows a transfer request from a priority processing device to be given priority among transfer requests from two types of processing devices that randomly generate data transfer requests.

[Summary of the invention]

In the present invention, the presence or absence of a transfer request is scanned from the priority side, and transfer requests on the non-priority side can be fully executed only when there is no transfer request on the priority side. however,
In this case, if transfer requests from the priority side are issued consecutively, the transfer requests from the non-priority side in between are not executed and are kept waiting, so the transfer request from the non-priority side is always executed once when the transfer operation on the priority side ends. This makes it possible to

[Embodiments of the invention]

FIG. 1 is a block diagram showing the configuration of a system to which the present invention is applied. In FIG. 1, 1 and 2 are processing devices that generate data transfer requests, and the processing device 1 side is the high priority side. Further, 3a and 3b are two-stage registers that accept transfer requests from the processing device 1, 6a is on the previous stage side, 3
b is the rear stage front 1. 4 is a register that accepts a transfer request from the processing device 2, 5 is an AND gate, and 6 is a scan that checks whether or not registers 3b and 4 have accepted a request, and sends a gate signal to the AND gate 5 after checking register 3b. A switching circuit 7 switches the data lines from the processing devices 1 and 2 by a switch of the scanning circuit 6, and a processing device 8 performs a transfer operation with the processing device 1 or 2.

FIG. 2 shows the operation flow of FIG. 1. Hereinafter, the operation shown in FIG. 1 will be explained in detail using FIG. 2.

The scanning circuit 6 first checks whether the register 3b has received a transfer request (step 101).

If there is an acceptance, the processing device 1 is connected to the processing device 8 by the switching circuit 7 and all data transfer operations of the processing device 1 are executed (102). After execution, the process returns to the check operation of the register 3b. Also, if there is no reception, please use ANDGATE 5.
A gate signal is sent to (105). If the transfer request is accepted by the register 5a by this gate signal, the transfer request is taken over by the register 3b.

Next, it is checked whether or not the transfer request is accepted in the register 4 (104). If there is an acceptance here, the switching circuit 7 connects the processing device 2 to the processing device 8 and executes the data transfer operation of the processing device 2. (1OS) After execution, the operation returns to checking the register 3b. Also, if there is no reception, the process returns to the check operation of the register 3b.

In Figure 1, transfer request reception on the priority side uses register 3.
The purpose of having two stages, a and 3b, will be explained. The disadvantage of the one-stage configuration is that the scanning circuit 6 always checks the registers on the priority side first, so if the frequency of transfer requests from the priority side is high, the transfer operation only on the priority side will be executed, and the transfer operation on the non-priority side will be executed. The processing device 2 continues to wait for a long time. Therefore, in order to be able to perform non-priority transfer only once at the break in the transfer operation of the priority-side processing device 1, the registers for receiving transfer requests on the priority side are configured in two stages. The operation will be explained using FIG. 3, which is an explanatory diagram of the operation of FIG. 1. In FIG. 3, 1.2 indicates the operating state of the processing device 1.2, and 5a, 3b, and 4 indicate the register 5, respectively.
a, 5b.

4 indicates the acceptance status of the transfer request, t indicates time, t,
~t,4 indicates the time of the state change point. The example in FIG. 5 shows the execution status of the transfer operation when the transfer request from the processing device 1 is at t, tB and the transfer request from the alpha processing device 2 is at position 16.

The explanation for time t to "14" is shown below.

The transfer request i3a of tl;1 is accepted.

I checked the reception for t2; 3b, but there was no reception.

t3: AND gate 5 is opened and the state of 3a is taken over to 31] (3b is also in the reception state).

t4; I checked the reception on 4, but there was no reception.

t5i 1 transfer operation starts when 5b is accepted.

Receive the transfer request ft4 at t6;2.

3a and 3b are also reset when the transfer operation of tl;1 is completed.

tB; A transfer request of 1 occurs immediately and is accepted at 3a.

I checked the reception of t, i 3b, but there was no reception.

T. ;Opens the AND gate 5 and takes over to the state Q3b of 3a (3b is also in the reception state).

t, 1; The reception of 4 is checked and the transfer operation of 2 is started.

t1□; Transfer operation of 2 is completed and 4 is also reset.

”+s　i　1 transfer operation starts at the reception leg of 5b.

t, 4; When the transfer operation of 1 is completed, 3a and 3b are also reset.

It can be seen that even if the transfer requests from the processing device 1 on the priority side continue in succession as in the operation example shown in FIG. 6, the transfer requests from the processing device 2 on the non-priority side can also be processed.

〔Effect of the invention〕

According to the present invention, even when data transfer requests are randomly generated from two types of processing devices, the transfer request from the priority side can be executed preferentially, and the transfer request from the non-priority side can also be executed for a long time. A transfer control method that does not require waiting can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram according to an embodiment of the present invention, FIG. 2 is an operation flowchart of FIG. 1, and FIG. 3 is a diagram for explaining the operation of FIG. 1. Explanation of symbols 1.2.8...Processing device

Claims (1)

[Claims] A method in which each processing device has a register that holds data transfer requests from two types of processing devices, scans the register output in order of priority, and transfers data to the processing device that made the transfer request. In this case, the register on the high-priority side has a two-stage configuration, and the first stage accepts data transfer requests from the processing device, and the second stage accepts data transfer requests based on the AND condition of the output of the first stage and the scan end information of the second stage. A transfer control method characterized in that the determination of the presence or absence of a transfer request from the priority side is performed by a register on the subsequent stage.