JPS6274151A - Divider for linear interpolator - Google Patents

Abstract

PURPOSE:To eliminate a selector, and to realize an LSI by operating a register in which small data are stored, as a dividend register, and operating a register in which large data are stored, as a divisor register. CONSTITUTION:In the beginning, two data are inputted to shift registers 3, 4, respectively. Output data from the shift registers 3, 4 are inputted to an adding circuit 5 which is operated as a subtracting circuit, and a carry output from the adding circuit 5 is inputted to a latching circuit being a discriminating circuit. By this latching circuit 7, the size relation of two input data is discriminated, and by inputting a control signal to the shift registers 3, 4, based on this result of discrimination, the contents of the shift register in which small data are stored are shifted. The result of division is obtained by executing a subtraction trial by the number of times determined by the contents stored in a counter 8.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a divider for a linear interpolator, and more particularly, to a divider for a linear interpolator that continuously draws straight lines connecting two points in a graphic display device. The present invention relates to a divider for a linear interpolator that is preferably used to make it possible to perform a linear interpolator.

<Prior art> In a graphic display device, when the coordinate values of two points are given, linear interpolation is performed between the two points to create a visually continuous straight line with consecutive dots on the display. It is required to draw it in such a way that it can be grasped as such.

For example, as shown in Figure 2A, when two points are given, the difference in coordinate values in the X direction is X1-XO, and the difference in coordinate values in the Y direction is Yl-YO. As is clear, cxi-xo)>(Yl-YO)F. Therefore, in this case, a change of 1 is given in the X direction, and (Y 1 - Y O)/(X 1
-X O), it is possible to draw a line segment with continuous dots, as shown by the circles in the figure.

Furthermore, as shown in Figure 2B, when two points are given, the difference in coordinate values in the X direction is X 2 - X O, the difference in coordinate values in the Y direction is Y 2 - Y O, etc. As is clear from the figure, (X2-XO)<('Y2-YO). In this case as well, the X direction is changed by 1, and the Y direction is (Y 2 - Y O)/(X 2
- It becomes a drawing state. Therefore, if you try to draw a line segment with continuous dots like Δ in Figure 2, Y7!
It is necessary to give a change of 1 in each of the five directions, and a change of (X 2 -X O)/(Y 2 -Y O) in the X direction.

In consideration of these points, conventionally, as shown in FIG. 3, the f-tactor
13) and 6, the 1F normalization circuit (12)
The i-tater Y is manually inputted to the selector (14) through the control signal of the wrap circuit (15) or l), and both selectors (
13) Output stomach data X and Y from (14) to h,
Dividend register (16) that registers shift 1~register
J′-Wrap the evening, Divisor 1 of C (17)
3. Then, the data of the dividend register (16) and the j'-ta of the divisor 1 register (17) are input to the shore line circuit (18) which is always given a carry power of 1. By manually performing the reduction n trial,
The dividend number is 1. The data in the dividend register (16) is updated by feeding back the nojister (16) and inputting -11/ri1 output data to the dividend register (16), and the cotton reduction trial is repeated 1!
1, which is designed to be able to
The output data from 18) is inputted into the quotient register (19) as a quotient, inputted into the dividend register (1G), and then inputted into the quotient register (1G), and further written as 1 in the quotient register (15).
It is also inputted to make the data X and Y be separated by size v11. Note that (20) is a counter C for controlling the number of decrement trials.

<Problems to be solved by the invention> - G. The conventional linear interpolator divider has a selector (13)
By (14), it is possible to select the data X and Y and enter the dividend register (16) and divisor register (17) manually, so the dots are always in a continuous state regardless of the coordinate values of the two points. It is possible to draw a line segment, but the dividend 1 register (16) and the divisor register (
17) is always fixed, the pair of selectors (13) and (14) is controlled by the magnitude relationship of both data.
)is necessary. And this selector (13) (14
), as the bit width of both data becomes larger, it is necessary to use a larger wiring capacity (for example, if the bit width of each f-t is 16 bits, , all′
IsI
The problem is that it is very difficult to convert.

In addition, the 1-no register in which the above-mentioned 1''-ta X and Y are stored is:
Since the function of C is fixed from the beginning as dividend 1 register and divisor register, depending on the result of the initial size determination, the dividend register (16) and divisor 1 register (17) can be recalculated. Store L2, and after that, reduce the required number of trials (“J Nawana (J must,
In view of the above-mentioned problems, this invention solves the problem that the time required to perform the removal operation becomes longer overall. The present invention aims to provide a linear interpolator divider which can reduce the wiring capacity i by eliminating the need for one noctor, and which can be easily integrated into an LSI.

<Means for solving problem y-gen> In order to achieve the above goal 1), the linear interpolator divider of the present invention consists of registers Shift 1 to Shift 1 to which registers are each input manually with two pieces of data. At the same time, it is possible to feed back the subtraction result from the subtraction circuit to both registers, and furthermore, it is possible to determine the magnitude of both data, and to output a control signal that causes only the register storing small data to act as a shift register. It has a circuit.

However, both of the shift registers may be input with data converted into floating point format from the beginning.

In the linear interpolator divider with the above configuration, the subtraction circuit performs subtraction with the two data input to the shift register, and the carry output from the subtraction circuit is input to the discrimination circuit. Therefore, by determining the magnitude relationship between both data and manually applying a control signal to the register based on the determination result, it is possible to operate the register storing small data as a shift register.

Therefore, the register that stores small data will operate as the dividend register, and the register that stores large data will operate as the divisor register.After that, they will operate in the same way as a conventional linear interpolator divider. to obtain the required division unity.

Further, it is preferable if both of the shift registers are inputted with data converted into a floating point format from the beginning, since data can be stored in the shift registers only once.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram showing an embodiment of a linear interpolator divider according to the present invention.

One data X is normalized by a normalization circuit (1) and inputted to one shift 1 register (3),
The other data Y is normalized by a normalization circuit (2) and input to the other shift register (4). Then, the output data from both shift registers (3) [4] is transferred to an adder circuit (5) which is always input with a carry value of 1 and operates as a subtracter circuit (the mantissa part of the data expressed in floating point format, and The result of subtraction from the adder circuit (5) can be fed back to both shift registers (31 (41). Furthermore, the adder circuit (5) The carry output of .And this latch circuit (different control signals from the sword (Q output and 0
output] j) is selectively input to the shift register (3) ('I). Note that (8) is input to the adder circuit (5).
) is a counter for controlling the number of subtraction attempts.

According to the linear interpolator divider having the above configuration, for example, the difference in coordinate values between two points in the X-axis direction shown in FIG. If the difference in coordinates between two points in the axial direction is input to the normalization circuit (2) as data Y, proper linear interpolation can be performed by operating as follows.

The details will be explained below.

First, data
At the same time, the data Y is converted by the normalization circuit (2) into floating point type data Y- and stored in the shift 1 register (4).

By inputting the data X'' and Y' to the adder circuit (5), the magnitude comparison of the mantissa part and the exponent part are simultaneously performed, and a carry output indicating the result of the magnitude comparison is sent to the latch circuit (5). This latch circuit (power) inputs the mutually different Q output signals and Q output signals to the control terminals of shift 1 register [3H'll, so -ri is input to shift 1 register [3H'll]. One register operates as a register, and the other operates as a register that only latches data.

That is, the side that operates as shift 1 to register becomes the dividend register, and the other side acts as the divisor register.

Therefore, from now on, by inputting the contents of both shift registers (3) f41 to the adder circuit (5), a subtraction trial is performed, and the shift registers are Shifting the contents of the side that operates η, or operating as a shift register, selectively moves the []-do of the reduction result to the side that reverses, and sets the output of the above key P as the quotient to the quotient register (6 ) stored in 4ru1
After , the result is obtained by performing a number of decrement trials determined by the contents stored in the counter (8).

To explain more specifically, if linear interpolation is performed as shown in FIG. 2, X=X1-XO, Y-Y 1-
Since Y O and X > Y, the shift register (4) operates as a 1-register, and the seed register (3) latches the f-ta (operates like a register of J, The result of dividing Y/X by p can be obtained in the quotient register 1G). .

In addition, when performing linear interpolation as shown in Figure 2B,
Since X=X2-XO, Y=Y2-YO, and X<Y, shift 1-register (3) operates as shift 1-register, and shift register (4) only latches data. The register operates and the quotient 1 register (6) receives
/Y division result can be obtained.

In the case of the above embodiment, shift register f31 (/1
Since the transfer of data to 1] only needs to be performed once, the time required for transferring 11.1 of data from 1 to 1 is reduced compared to the conventional example.
'j ('ij = C'-63゜In addition, (in the second embodiment, t'i <: niwana G] to determine the size of the Iy number part and the exponent part at the same time, then 2
．． ffi et al. Therefore, the degree of complexity is small (11
Mi, conventionally necessary-C・A・)! , it is possible to simplify the configuration of the divider for the linear interpolator.

In addition, in the example of 1 zu 10, Lt, shift 1-register (3) from the beginning (Explanation 1 for the case where 41 and 2 dynamic decimal numbers r:, < are converted to the format and I j'- data are stored) l,
-, each i1- realization circuit +1 + (21 has a built-in l letter, and J-1-tata
3+ ('l) operation and floating point mountain type Jt
Shift 1 to register (
3) Which action stored in (4) is selectively performed? ”
J and B are ready.

In this case, the 1F realization circuit (fl) (2) has a built-in resistor, so the configuration is different. You may think that it is Ltl, but the built-in selector only allows you to select whether to output the data X and Y as they are or to output the normalized f-data X-1Y''. Therefore, compared to the selector in the conventional example, it is possible to significantly reduce the 1!i! ,
Simplification of the configuration corresponding to this part can also be achieved.

However, in this case, after writing the data X and Y to the Schiffmill register +31 f4) and determining the size,
Since the data X", Y- must be loaded into the Schiffmill register (3) (41), the data transfer time becomes longer than in the above embodiment, but there is no particular disadvantage.

<Effects of the Invention> As described above, the present invention makes it possible to select the divisor and dividend without using a reflector when performing division based on the coordinate data of two points. Therefore, the wiring weight can be reduced, the structure of the C linear interpolator divider can be simplified as a whole, and LSI integration can be achieved.

In particular, the data that has been converted to floating point Tebou expression from the beginning is 11
In the case of ``-'', the ``11-'' of ``-'' only needs to be done once, which has the effect of shortening the time required for the division of C as a whole.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an embodiment of the divider for linear interpolators according to the present invention, Fig. 2 is a diagram explaining the relationship between the two conditions for performing linear interpolation, and Fig. 3 is a diagram for the conventional linear interpolator. J block 1-1 diagram showing the Q remover.

Claims (1)

[Claims] 1. Dividend data in dividend register and division The divisor data of the number register and the subtraction circuit When you input and perform a subtraction trial, Then output the carry signal as a quotient and Furthermore, the subtraction result from the subtraction circuit is transferred to the dividend level. By giving feedback to the A straight line that causes the required number of subtraction attempts. In the interpolator divider, both registers above In addition to configuring the data with shift registers, The subtraction result from the subtraction circuit is stored in both registers. Feedback is possible and further The size of data is determined and small data is stored. Shift only the registers that are Outputs a control signal to act as a controller. A straight line characterized by having a discrimination circuit Divider for interpolator. 2. Both shift registers are floating small from the beginning. The data converted to the number-point format is input. Claim 1 above Divider for the linear interpolator described.