JPS60103483A - Clipping processing circuit - Google Patents

Abstract

PURPOSE:To perform calculation with just a single instruction and to secure the application to calculation of an intersecting point using a middle point method, by switching an address circuit between different addresses when the clock signals are set at low and high logic levels. CONSTITUTION:When a clock has a rise and is set at a high level, addresses A and B are outputted to address buses 25a and 25b. Then A and B registers 19 and 21 output data (a) and (b) to an operator 23 via latches 20 and 22. The operator 23 outputs the arithmetic result of (a+b) to a shifter 24, and the shifter 24 delivers the result obtained from the right shift by a bit, i.e., (a+b)/2. This output is sent to both registers 19 and 21. When the clock has a fall and is set at a low level, the contents of buses 25a and 26b are written to a designated address.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clipping circuit suitable for performing an intersection calculation method using a midpoint method in a graphic display device.

The graphic display device has the configuration shown in FIG. Graphic data transferred from the host computer 1 is stored in a line segment buffer 3 through a channel adapter 2, and sent to a matrix circuit 5 through a graphic processor 4 containing data to be displayed.

There is no processing for enlargement, reduction, rotation, or translation here.
The signal is sent to the clipping circuit 6. The clipping circuit 6 extracts only the data of the portion that falls within the display area of the screen from the processed data and sends it to the direct helix generation circuit jj57. Here, linear interpolation is performed on the given data, and after the data is temporarily stored in the image memory 8, it is converted into a video signal by the video signal conversion circuit 9, and a figure is displayed on the ORT Q.

Here, the clipping process using the intersection meter (2) based on the midpoint method will be briefly explained.

Figure 6: Extracted portion of ORT 10 from Figure 1
), it is assumed that there is a house figure abcdefQ(L) in the mouth-shaped display area ABOD of the screen 11. If only the figure display area ABOD is shown, it becomes as shown in FIG. 6 (6). At this time, the first When the house figure is enlarged and translated by the matrix circuit 6 shown in the figure, the house figure becomes αα-bb -ca-dd-g as shown in Fig. 6(C).
g -ff -(#-αG, figure display area ABO
Since it protrudes from D, it is necessary to cut out a part of the figure. In Figure 6 (C), Be and IIg
- It is necessary to select two points, the intersection of hh and the intersection i of AD and QfJ -aa, and display only the figure of h -ff - yrt -t - The process of cutting out this figure is the clipping process, One of the ways to find intersections like () is the midpoint method.

To give an example of the midpoint method, in Fig. 6 (,Z), there are two points P1sP! When n is given, suppose we want to find the intersection Pc with @mt. First, the midpoint of P and P2 is P@ = (=
(PI + "t) / 2). Since this point does not intersect with t, next P, and the midpoint of P8, P4 (=
(Fs +P*)/2). Since this also does not intersect with t, the next step is P, and the midpoint of PI Ps (= (PI
+ ”s ) / 2). Thereafter, similarly Pn = (
Pn+Pn! )/2 and the midpoint between the two points, the midpoint Pn will eventually converge to the intersection with the straight line t, that is, p6. In this way, by continuing to find the midpoint of two points and converging them to one point, the midpoint method can be used to calculate the intersection point. In this method, Pn= (Pn-, +Pn-
, )/2, it can be obtained by a simple method of adding two numbers and multiplying by 1/2 (in terms of circuitry, just shift 1 bit to the right), and is characterized by high-speed calculation. Yes, there are other methods besides the midpoint method, such as solving plane equations, but they require remainders and divisions, which slows down the calculation speed.

Next, considering the circuit configuration, conventionally a circuit configuration as shown in FIG. 2 has been used.

Reference numeral 3 is a register for storing data, and an address circuit 14 specifies the end address of the memory. 15,
16Pl: Holds the data in register 13 with a latch.

15 and 16 are AA-latch and B latch, respectively, and the outputs of 1 and 2 are respectively arithmetic unit (hereinafter referred to as ALU) 1.
Two inputs 17-1, 17-2, and 7 are input. The calculation result is input to the shifter 18. In addition to outputting the input as is, the shifter 18 can also shift the input one bit to the right or left and output it.

By the way, in binary calculations, one pit shift to the right is 1/2.
A double left 1-bit shift is a doubling. shifter 1
The output of 8 is returned to register 13 again.

A circuit configuration like this only requires one set of registers, two latches, and an ALU (generally a shift
Microprocessors in particular have built-in components equivalent to latches 15 and 16 in addition to ALU 17, so all you need to do is prepare external components equivalent to register 13. It's a method.

Now, let's consider calculation using the midpoint method using this circuit configuration. For example, the calculation 1− Ps ” CP! + Pl )/22− PI as mentioned earlier in the explanation of the midpoint method
= (Pa + Pt) / 2n, Pyz= C
Consider Pn-1+Pn-t)/2.

(2) Take out P1 from the register 13 and input it to the port A of the ALU 17 through the A-latch 15.

(2) Take out P2 from the register 13 and input it to the baud of ALP17 through the B-latch 16.

■ALD 17 TeP 1-1- P , the result of performing the operation and shifting 1 bit to the right with thick 18 (:
p1+P, )/2 is stored in the register 13 as Pa.

(2) Release P8 from the register 13 and input it to the baud A of the ALU 17 through the A-latch 15.

(2) Take out p from the register 13 and input A:L U 17 baud) BK large through the B-latch 16.

■ALU 17 calculates PI -1-pl, and thick 18 shifts the result by 1 bit to the right (F8+
P1]/2 is stored in the register 13 as number p.

Thereafter, in the same way, P n = (P n + 1 +
Subtract F%-3)/2.

As mentioned above, such a circuit configuration can be easily realized by simply providing one set of external registers, but on the other hand, PtL=(P
Even in the case of calculation n-1+Pn-2)/2, it takes three steps. Even simple calculations cannot be done with one command, so
It is unsuitable when trying to perform high-speed calculations using the midpoint method.

Therefore, the present invention aims to eliminate this problem and provide a clipping circuit suitable for calculating intersections using the midpoint method.

Hereinafter, the present invention will be explained in detail based on the drawings.

The third factor is a circuit block diagram of an embodiment of invention X. 1
9, 21 Rough in hare register, respectively yl, AV
X) Star and B registers. A register and B register are low active WE terminal 19 (L, 21α
This terminal 19α, 21cL has a logic level of 10.
It is set up so that a write operation is performed when the flag is -1, and a read operation is performed at other times. As an example, in this circuit, a clock is used for the WE terminals 19α and 21α. The outputs of the A register and the B register are sent to the A latch 20 and the B latch 22. The outputs of the A latch mark and the B latch 22 hold the data until the next input, and each output is AL
Input terminals of U23, A port 23α, B boat:
3b. The ALU 23 performs necessary calculations based on the inputs from the A port α and the B port 23b, and inputs the results to the output shifter 24.

Shifter M has four functions, one pit left and right. In binary, a 1-bit shift to the left is doubled, and a 1-bit shift to the right is 1 no 2.
Since it is equivalent to multiplying, the calculation result of AIIU25 can be doubled or 1
It can be multiplied by 2. Shifter Sae's output is 19 again
, 21 are returned to the A and B registers. The circuit block 5, which is surrounded by a one-dot chain line -f'L7, is an address circuit block, and the address of the A register of 19 is sent to the address bus 5bK by 61+address bus 5α! Specify the address of the B register in 21.

In FIG. 4, the detailed circuit of the final address circuit block 5 is marked with -. The S class of addresses that can be specified during one clock (the minimum time to drive the circuit for one operation) is A.
There are three types: , B, and O. Address A is a multiplier (
Nine inputs are input to the A multiplexer (hereinafter referred to as A-MPX)'25d through 25G (hereinafter referred to as MPY).

Finished address B is input to MFY25e and MFY25/p%
Address B via MFY25g is B-MPX25J
It is input to the A input of 7. Address O is input to MPY255.

The outputs of MPX25f and MPY25h are connected by wired ORB, A-MPX2Sd%B-MPX251JOB
entered into the input. A-MPX25. d and B-MP! 2
Whether the input of B-Input of 5g is address B or address C is M P Y 25 f s M P
It is switched by low active output pull (om) terminals 254 and 25j that control the output of Y25h. As an example, here the 30I signal is 011!
1I2i! Child? 5j, and enters 25- through the inverter 25k, so when the 1P multiplied signal 60-" is at the logic level, the output of MPY25h, the output address C, becomes MPx25d.
, 25I's B-must be entered manually, (2) When the P signal is at the logic level of ''/1-1, MypXBd, 95
9's B-enpwt will contain the dress B. A + M F X25d and B-MPX25f
9 has two types of inputs, 8-human power and B-human power, and has the function of selecting and outputting either input, but the selection terminal 25t and 25m is up to you to choose which input. It's decided. A certain signal, here a clock is used, and when this clock is 171", 8-human power is selected, and when this clock is 10", B-human power is selected. FIG. 5 shows the state.

Let us now consider the case of calculating C←(α+b)/2 as described in the conventional example.

When the clock reaches the rising V'''' no-bell, the state shown in Fig. 4 (
7) A-MPX25d and B-MP! ? Since the terminals 25Ls and 25m are 1NO, they output the signals that enter the input terminals, that is, the address A and address B, to the address buses 5α and 256. Therefore, the A register 19 and the B register 21 in FIG. , address A, respectively.
The contents of address B, f, and data α and b are output, and are input to the ALU 23's A boat, α, B baud)Z(6) via the next latch 20.22.
The calculation result of b) is sent to the shifter 24 (usually the shifter is AL,
Shifter Sae outputs V(α+b)/2 as a result of shifting 1 bit to the right. Next, when the clock falls and reaches 10 levels, the 11 terminals 19α and 21α of the A register 19 and B register 21 become 10-”, so the register receives the signal from the shifter at the specified address. Write data (α+b)/2.The addresses specified here are
The contents are as follows. Looking at Figure 4, MPX25.9, B-
Since the clock is always input to the sector V section terminal 25t of MPX2Sd, when the registers 19 and 21 perform a write operation, the A-MPX95, 9, BMFX? The contents of B in 5d are address bus 5α.

25b. In other words, at this time K
? , the OF signal is 10'' and M P Y 25
7)” V SuO75S, A-MPX25d,
When input to B-InPut of B-MPX25II, A register 19 and B-register 21 in FIG. 3 write (A + B)/2 to address O. Therefore, in one clock, that is, in one program instruction, C←(A+B)/
2 calculations can be performed.

As mentioned above, conventionally it required three program instructions to perform the same calculation C←(A+B)/2, but with this circuit example, it is now possible to perform the calculation with one instruction. . In this method, an independent register is provided for each input of the ALU, and a different address can be selected for each register, and different addresses can be continuously specified when reading from and writing to the register. Depends on the effect of making it possible.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of the configuration of a graphic display device, Fig. 2 is a conventional circuit diagram, Fig. 3 is a circuit diagram of an embodiment, and Fig. 4 is an address circuit diagram of the embodiment circuit. be. 50 is an explanatory diagram showing a state when a different address is selected, and FIGS. 6(B) to Cd) are explanatory diagrams showing the clipping process of FIG. 1. 19., A register addition 1. A latch 21°, B register 22. , B latch 23. , ALU 24°, shifter 95c, 25e, 9Sf, 2Sh
, , Marf Plier 25d, 25110. Multiplexer 25 and above Inverter Applicant Seiko Electronic Industries Co., Ltd. Agent Patent Attorney Mogami Figure 2 Figure 3

Claims (1)

[Claims] A computing unit, a register corresponding to each input of this computing unit,
In a clipping processing circuit consisting of an address circuit that specifies the address of this register, the end address circuit differs in its output when the clock signal is in a binary state of logic level 60-' and logic level "high". 43: A clipping processing circuit characterized by having seven functions.